參數(shù)資料
型號: SC16C2550B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
中文描述: 5伏,3.3伏和2.5伏兆5雙UART /秒(最大),16字節(jié)的FIFO
文件頁數(shù): 9/42頁
文件大?。?/td> 200K
代理商: SC16C2550B
Philips Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Product data
Rev. 02 — 14 December 2004
9 of 42
9397 750 14449
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6.
Functional description
The SC16C2550B provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data
stream into parallel data that is required with digital data systems. Synchronization for
the serial data stream is accomplished by adding start and stop bits to the transmit
data to form a data character (character orientated protocol). Data integrity is insured
by attaching a parity bit to the data character. The parity bit is checked by the receiver
for any transmission bit errors. The electronic circuitry to provide all these functions is
fairly complex, especially when manufactured on a single integrated silicon chip. The
SC16C2550B represents such an integration with greatly enhanced features. The
SC16C2550B is fabricated with an advanced CMOS process.
The SC16C2550B is an upward solution that provides a dual UART capability with
16 bytes of transmit and receive FIFO memory, instead of none in the 16C2450. The
SC16C2550B is designed to work with high speed modems and shared network
environments that require fast data processing time. Increased performance is
realized in the SC16C2550B by the transmit and receive FIFOs. This allows the
external processor to handle more networking tasks within a given time. For example,
the ST16C2450 without a receive FIFO, will require unloading of the RHR in
93 microseconds (this example uses a character length of 11 bits, including start/stop
bits at 115.2 kbit/s). This means the external CPU will have to service the receive
FIFO less than every 100 microseconds. However, with the 16 byte FIFO in the
SC16C2550B, the data buffer will not require unloading/loading for 1.53 ms. This
increases the service interval, giving the external CPU additional time for other
applications and reducing the overall UART interrupt servicing time. In addition, the
four selectable receive FIFO trigger interrupt levels is uniquely provided for maximum
data throughput performance especially when operating in a multi-channel
environment. The FIFO memory greatly reduces the bandwidth requirement of the
external controlling CPU, increases performance, and reduces power consumption.
The SC16C2550B is capable of operation up to 5 Mbit/s with a 80 MHz clock. With a
crystal or external clock input of 7.3728 MHz, the user can select data rates up to
460.8 kbit/s.
The rich feature set of the SC16C2550B is available through internal registers.
Selectable receive FIFO trigger levels, selectable TX and RX baud rates, and modem
interface controls are all standard features. Following a power-on reset or an external
reset, the SC16C2550B is software compatible with the previous generation,
ST16C2450.
6.1 UART A-B functions
The UART provides the user with the capability to bi-directionally transfer information
between an external CPU, the SC16C2550B package, and an external serial device.
A logic 0 on chip select pins CSA and/or CSB allows the user to configure, send data,
and/or receive data via UART channels A-B. Individual channel select functions are
shown in
Table 3
.
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SC16C2550B_07 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
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SC16C2550BIA44,512 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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