參數(shù)資料
型號(hào): SC16C2550B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
中文描述: 5伏,3.3伏和2.5伏兆5雙UART /秒(最大),16字節(jié)的FIFO
文件頁(yè)數(shù): 25/42頁(yè)
文件大小: 200K
代理商: SC16C2550B
Philips Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Product data
Rev. 02 — 14 December 2004
25 of 42
9397 750 14449
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
7.9 Scratchpad Register (SPR)
The SC16C2550B provides a temporary data register to store 8 bits of user
information.
7.10 SC16C2550B external reset condition
1
MSR[1]
DSR
[1]
Logic 0 = No DSR change (normal default condition).
Logic 1 = The DSR input to the SC16C2550B has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
CTS
[1]
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C2550B has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
0
MSR[0]
Table 19:
Bit
Modem Status Register bits description
…continued
Symbol
Description
Table 20:
Register
IER
FCR
ISR
LCR
MCR
LSR
MSR
SPR
DLL
DLM
Reset state for registers
Reset state
IER[7-0] = 0
FCR[7-0] = 0
ISR[7-1] = 0; ISR[0] = 1
LCR[7-0] = 0
MCR[7-0] = 0
LSR[7] = 0; LSR[6-5] = 1; LSR[4-0] = 0
MSR[7-4] = input signals; MSR[3-0] = 0
SFR[7-0] = 1
DLL[7-0] = X
DLM[7-0] = X
Table 21:
Output
TXA, TXB
OP2A, OP2B
RTSA, RTSB
DTRA, DTRB
INTA, INTB
Reset state for outputs
Reset state
Logic 1
Logic 1
Logic 1
Logic 1
3-State condition
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