參數(shù)資料
型號(hào)： SC16C2550B
廠商： NXP Semiconductors N.V.
英文描述： 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
中文描述： 5伏，3.3伏和2.5伏兆5雙UART /秒（最大），16字節(jié)的FIFO
文件頁(yè)數(shù)： 20/42頁(yè)
文件大?。?/td> 200K
代理商： SC16C2550B
Philips Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Product data
Rev. 02 — 14 December 2004
20 of 42
9397 750 14449
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 12:
Bit
7-6
Interrupt Status Register bits description
Symbol
Description
ISR[7-6]
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are
not being used in the 16C450 mode. They are set to a logic 1
when the FIFOs are enabled in the SC16C2550B mode.
Logic 0 or cleared = default condition.
ISR[5-4]
Not used.
ISR[3-1]
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see
Table 11
).
Logic 0 or cleared = default condition.
ISR[0]
INT status.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
5-4
3-1
0
Table 13:
Bit
7
Line Control Register bits description
Symbol
Description
LCR[7]
Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch enabled.
LCR[6]
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0
state). This condition exists until disabled by setting LCR[6] to a
logic 0.
Logic 0 = no TX break condition (normal default condition)
Logic 1 = forces the transmitter output (TX) to a logic 0 for
alerting the remote receiver to a line break condition.
LCR[5-3]
Programs the parity conditions (see
Table 14
).
LCR[2]
Stop bits. The length of stop bit is specified by this bit in
conjunction with the programmed word length (see
Table 15
).
Logic 0 or cleared = default condition.
LCR[1-0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
Table 16
).
Logic 0 or cleared = default condition.
6
5-3
2
1-0
相關(guān)PDF資料
PDF描述
SC16C2550BIN40 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
SC16C2550IA44 Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SC16C2550B_07 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
SC16C2550BIA44 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C2550BIA44,512 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C2550BIA44,518 功能描述:UART 接口集成電路 2CH. UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C2550BIA44,518-CUT TAPE 制造商:NXP 功能描述:SC16C2550B 5 V 3.3 V and 2.5 V Dual UART 5 Mbit/s w/ 16-byte FIFOs - PLCC44
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