
C165UTAH
System Programming
Data Sheet
487
2001-02-23
The EXTP (extend page) instruction
allows switching to an arbitrary data page for 1...4
instructions without having to change the current DPPs.
EXTP
R15, #1
;The override page number is stored in R15
MOV
R0, [R14]
;The (14-bit) page offset is stored in R14
MOV
R1, [R13]
;This instruction uses the std. DPP scheme!
The EXTS (extend segment) instruction
allows switching to a 64 KByte segment
oriented data access scheme for 1...4 instructions without having to change the current
DPPs. In this case all 16 bits of the operand address are used as segment offset, with
the segment taken from the EXTS instruction. This greatly simplifies address calculation
with continuous data like huge arrays in “C”.
EXTS
#15, #1
;The override seg. is 15 (0F’0000H..0F’FFFFH)
MOV
R0, [R14]
;The (16-bit) segment offset is stored in R14
MOV
R1, [R13]
;This instruction uses the std. DPP scheme!
Note:
Instructions EXTP and EXTS inhibit interrupts the same way as ATOMIC.
Short Addressing in the Extended SFR (ESFR) Space
The short addressing modes of the C165UTAH (REG or BITOFF) implicitly access the
SFR space. The additional ESFR space would have to be accessed via long addressing
modes (MEM or [Rw]). The EXTR (extend register) instruction redirects accesses in
short addressing modes to the ESFR space for 1...4 instructions, so the additional
registers can be accessed this way, too.
The EXTPR and EXTSR instructions combine the DPP override mechanism with the
redirection to the ESFR space using a single instruction.
Note:
Instructions EXTR, EXTPR and EXTSR inhibit interrupts the same way as
ATOMIC.
The switching to the ESFR area and data page overriding is checked by the
development tools or handled automatically.
Nested Locked Sequences
Each of the described extension instruction and the ATOMIC instruction starts an
internal “extension counter” counting the effected instructions. When another extension
or ATOMIC instruction is contained in the current locked sequence this counter is
restarted with the value of the new instruction. This allows the construction of locked
sequences longer than 4 instructions.
Note:
Interrupt latencies may be increased when using locked code sequences.
PEC requests are not serviced during idle mode, if the IDLE instruction is part of
a locked sequence.