
C165UTAH
Interrupt and Trap Functions
Data Sheet
131
2001-02-23
The bit-addressable Trap Flag Register (TFR) allows a trap service routine to identify the
kind of trap which caused the exception. Each trap function is indicated by a separate
request flag. When a hardware trap occurs, the corresponding request flag in register
TFR is set to '1'.
TFR (FFAC
H
/ D6
H
)
15
14
SFR
Reset Value: 0000
H
3
2
Note:
The trap service routine must clear the respective trap flag, otherwise a new trap
will be requested after exiting the service routine. Setting a trap request flag by
software causes the same effects as if it had been set by hardware.
The reset functions (hardware, software, watchdog) may be regarded as a type of trap.
Reset functions have the highest system priority (trap priority III).
Class A traps have the second highest priority (trap priority II), on the 3rd rank are class
B traps, so a class A trap can interrupt a class B trap. If more than one class A trap occur
at a time, they are prioritized internally, with the NMI trap on the highest and the stack
underflow trap on the lowest priority.
All class B traps have the same trap priority (trap priority I). When several class B traps
get active at a time, the corresponding flags in the TFR register are set and the trap
service routine is entered. Since all class B traps have the same vector, the priority of
Bit
Function
ILLBUS
Illegal External Bus Access Flag
An external access has been attempted with no external bus defined.
ILLINA
Illegal Instruction Access Flag
A branch to an odd address has been attempted.
Illegal Word Operand Access Flag
A word operand access (read or write) to an odd address has been attempted.
ILLOPA
PRTFLT
Protection Fault Flag
A protected instruction with an illegal format has been detected.
Undefined Opcode Flag
The currently decoded instruction has no valid C165UTAH opcode.
UNDOPC
STKUF
Stack Underflow Flag
The current stack pointer value exceeds the content of register STKUN.
STKOF
Stack Overflow Flag
The current stack pointer value falls below the content of register STKOV.
NMI
Non Maskable Interrupt Flag
A negative transition (falling edge) has been detected on pin NMI.
NMI
5
4
1
0
11
10
9
8
7
6
13
12
rw
rw
rw
rw
rw
-
-
-
-
rw
-
-
-
STK
UF
ILL
BUS
ILL
INA
ILL
OPA
PRT
FLT
UND
OPC
STK
OF
-
-
-
-
-
-
-
-
-
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