
C165UTAH
IOM-2 Interface Controller
Data Sheet
367
2001-02-23
16.5.4
Synchronous Transfer
While looping, shifting and switching the data can be accessed by the controller between
the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV).
The microcontroller access to the CDAxy registers can be synchronized by means of
four programmable synchronous transfer interrupts (STIxy) and synchronous transfer
overflow interrupts (STOVxy) in the STI register.
Depending on the DPS bit in the corresponding CDA_TSDPxy register the STIxy is
generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected time slot
(CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks.
A non masked synchronous transfer overflow (STOVx
0
y
0
) interrupt is generated if the
appropriate STIx
1
y
1
is not acknowledged in time. The STIx
1
y
1
is acknowledged in time if
bit ACKx
1
y
1
in the ASTI register is set to ’1’ one BCL clock (for DPS=’0’) or zero BCL
clocks (for DPS=’1’) before the time slot which is selected for the appropriate STOVx
0
y
0
.
If STIx
1
y
1
and STOVx
1
y
1
are not masked STOVx
1
y
1
is only related to STIx
1
y
1
(
see
example a), c) and d) of Figure 125
).
If STIx
1
y
1
is masked but STOVx
1
y
1
is not masked, STOVx
0
y
0
is related to each enabled
STIxy (
see example b) and d) of Figure 125
).
Setting the corresponding bits in the MSTI (Mask Synchronous Transfer Interrupts)
register masks the STIxy and the STOVxy interrupt. The interrupt structure of the
synchronous transfer is shown in
Figure 124
. Examples of the described synchronous
transfer interrupt controlling are illustrated in
Figure 125
. A read to the STI register
clears the STIxy and STOVxy interrupts.
.
Figure 124
Interrupt Structure of the Synchronous Data Transfer
CIC
MOS
4x
ST
HDLC
HDLC
CIC
MOS
4x
ST
IOMINT
STI11
STI10
ISTA
MASK
MSTI
STI
STI20
STI21
STOV10
STOV11
STOV20
STOV21
STI11
STI10
STI20
STI21
STOV10
STOV11
STOV20
STOV21
ACK11
ACK10
ASTI
ACK20
ACK21