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參數(shù)資料
| 型號(hào)： | SAA7785 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | ThunderBird Avenger（TM） PCI Audio Accelerator(雷鳥Avenger（TM）PCI音頻加速器) |
| 中文描述： | 雷鳥復(fù)仇者（商標(biāo)）的PCI音頻加速器（雷鳥復(fù)仇者（商標(biāo)）的PCI音頻加速器） |
| 文件頁(yè)數(shù)： | 50/68頁(yè) |
| 文件大?。?/td> | 1303K |
| 代理商： | SAA7785 |
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ThunderBird Avenger
TM
PCI Audio
Accelerator
SAA7785
Philips Semiconductors
Preliminary Specification
1999
Nov 12
50
Note: An RC indicates that this bit can be reset to 0 by writing a 1. Writing a zero leaves this bit unchanged.
TABLE 38
Revision ID Register - REVISION (RO)
D7
D6
D5
D4
D3
D2
D1
D0
F_
BK2BK
UDF
MHz66
R
R
R
R
R
POR Value
1
0
0
0
0
0
0
0
Bit
Name
R/W
Function
15
R_PERR
RC
Received Parity Error: When set to 1, this bit indicates that the SSA7785
ThunderBird Avenger, function 1 has detected a PCI bus parity error at
least once since this bit was last reset.
14
S_SERR
RC
Signalled System Error: When set to 1, this bit indicates that the SSA7785
ThunderBird Avenger, function 1 has reported a system error on the
SERR# signal at least once since this bit was last reset.
13
SM_ABORT
RO
Signalled Master Abort: The SSA7785 ThunderBird Avenger, function 1,
does not act as a master.
12
RT_ABORT
RO
Received Target Abort: The SSA7785 ThunderBird Avenger, function 1
does not act as a master.
11
ST_ABORT
RC
Signalled Target Abort: When set to 1, this bit indicates that the SSA7785
ThunderBird Avenger, function 1 has signalled a target abort at least once
since this bit was last reset.
10:9
DEVSEL_TM
G
RO
DEVSEL Timing: This field indicates the timing of the DEVSEL output (when
a PCI master is accessing a SSA7785 ThunderBird Avenger, function 1
resource). It always returns 01 (Bin).
00 = Fast
01 = Medium (Default Timing)
10 = Slow
8
S_PERR
RO
Signalled Parity Error: The SSA7785 ThunderBird Avenger, function 1,
does not act as a bus master.
7
F_BK2BK
RO
Always returns 1 to indicate support of fast back to back cycles when the
SSA7785 ThunderBird Avenger, function 1 is the target.
6
UDF
RO
User Definable Features. Always returns 0.
5
MHz66
RO
66 MHz Capable. Always returns 0.
4:0
R
RO
Reserved. These bits always return zero.
PCI CFG 1
D7
D6
D5
D4
D3
D2
D1
D0
Offset 08h
REVISION_ID[7:0]
POR Value
0
0
0
0
0
0
0
0
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