參數(shù)資料
型號: SAA7707H
廠商: NXP SEMICONDUCTORS
元件分類: 數(shù)字信號處理
英文描述: Shaft; Style: 1 - light; Applicable Model: LE-P / LEL-W
中文描述: 0-BIT, 36.86 MHz, OTHER DSP, PQFP80
封裝: 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80
文件頁數(shù): 6/48頁
文件大小: 244K
代理商: SAA7707H
1997 May 30
6
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
7
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
V
DACNL
CINT
FM
1
2
3
internal ground reference voltage for the level ADC
level ADC switch-mode integrator connector
FM level input; via this pin, the level of the received FM radio signal is fed to the
CDSP, the level information is required to enable correct functioning of the weak
signal behaviour
AM level input; via this pin, the level of the received AM radio signal is fed to the
CDSP
ground supply 1 for the DACs digital circuitry
ground supply for the DACs analog circuitry
positive supply 1 for the DACs digital circuitry
positive supply for the DACs analog circuitry
analog audio current output for rear right speaker
analog audio voltage output for rear right speaker
analog audio current output for rear left speaker
analog audio voltage output for rear left speaker
internal reference current source input for the DACs
ground supply for DAC output operational amplifiers
positive supply for DAC output operational amplifiers
analog audio current output for front right speaker
analog audio voltage output for front right speaker
analog audio current output for front left speaker
analog audio voltage output for front left speaker
voltage input for the internal reference buffer amplifier of the DAC
activates the Power-on mute; timing is determined with an external capacitor
ground supply 2 for the digital circuitry
clock input for CD digital audio source (I
2
S-bus)
Word Select input for CD digital audio source (I
2
S-bus)
left/right data input for CD digital audio source (I
2
S-bus)
input to reset DSP core (active LOW)
external input data channel 1 (front) from extra DSP chip (I
2
S-bus)
external input data channel 2 (rear) from extra DSP chip (I
2
S-bus)
ground supply 9 for the digital circuitry
scan control (active HIGH)
I
2
S-bus selection for slave sub-address
asynchronous reset test control block (active HIGH)
shift clock test control block (active HIGH)
ground supply 7 for the digital circuitry
output data for extra external DSP chip (I
2
S-bus)
output clock for extra external DSP chip (I
2
S-bus)
word select input/output for extra external DSP chip (I
2
S-bus)
I
AM
4
I
V
SSD1
V
SSA
V
DDD1
V
DDA
RIOR
RVOR
RIOL
RVOL
I
ref(int)
V
SSO
V
DDO
FIOR
FVOR
FIOL
FVOL
V
ref
POM
V
SSD2
CDCLK
CDWS
CDDAT
DSPRESET
EXDAT1
EXDAT2
V
SSD9
TSCAN
A0
RTCB
SHTCB
V
SSD7
EXDAT
EXSCL
EXWS
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
O
O
O
O
I
O
O
O
O
I
I
I
I
I
I
I
O
O
I/O
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