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參數(shù)資料
| 型號： | SAA7707H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Shaft; Style: 1 - light; Applicable Model: LE-P / LEL-W |
| 中文描述： | 0-BIT, 36.86 MHz, OTHER DSP, PQFP80 |
| 封裝： | 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80 |
| 文件頁數(shù)： | 36/48頁 |
| 文件大?。?/td> | 244K |
| 代理商： | SAA7707H |
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1997 May 30
36
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
15 I
2
C-BUS CONTROL AND COMMANDS
15.1
Characteristics of the I
2
C-bus
The I
2
C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to V
DDD
via a pull-up resistor when connected
to the output stages of a microcontroller. Data transfer can
only be initiated when the bus is not busy.
15.2
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse, as changes in the data line
at this time will be interpreted as control signals.
The maximum clock frequency is 100 kHz (see Fig.16).
15.3
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P) (see Fig.17).
15.4
Data transfer
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’.
The device that controls the message is the ‘master’ and
the devices that are controlled by the master are the
‘slaves’ (see Fig.18).
15.5
Acknowledge
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master
generates an extra acknowledge-related clock pulse.
A slave receiver that is addressed must generate an
acknowledge after the reception of each byte. Also, a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter.
The device that acknowledges has to pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge-related clock pulse. Set-up and hold times
must be taken into account. A master receiver must signal
an end-of-data to the transmitter by
not
generating an
acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data
line HIGH, to enable the master to generate a STOP
condition (see Fig.19).
15.6
I
2
C-bus format
15.6.1
A
DDRESSING
Before any data is transmitted on the I
2
C-bus, the device
that should respond is addressed first. The addressing is
always done with the first byte transmitted after the START
procedure.
15.6.2
S
LAVE ADDRESS
(A0
PIN
)
The CDSP acts as a slave receiver or slave transmitter.
Therefore, the clock signal SCL is only an input signal.
The data signal SDA is a bi-directional line. The CDSP
slave address is shown in Table 6.
Table 6
Slave address
The sub-address bit A0 corresponds to the hardware
address pin A0, which allows the device to have 1 of 2
different addresses. The A0 input is also used in test mode
as a serial input of the test control block.
15.6.3
CDSP
WRITE CYCLES
The I
2
C-bus configuration for a WRITE cycle is illustrated
in Fig.22. The WRITE cycle is used to write in the IAC
register, the input selector control register and to initialize
or update coefficient values in XRAM or YRAM. The data
is transferred from the I
2
C-bus register to the DSP register
once every DSP cycle.
The I
2
C-bus interface circuitry in the SAA7707H requires
that the LOW period of the SCL line following the
acknowledge bit is at least 1/f
s
(in seconds); where f
s
is the
audio sampling frequency (in Hertz). This requirement
must be met for a single write operation and an
auto-incremental operation, but only applies to the
acknowledge bit following each DATA-L
(see Figs 20 and 21).
The data length is 2 or 3 bytes, depending on the
accessed memory. If the Y-memory is addressed the data
length is 2 bytes, If the X-memory is addressed the length
is 3 bytes. The slave receiver detects the address and
adjusts the byte length accordingly.
MSB
LSB
0
0
1
1
1
0
A0
R/W
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7708H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Car Radio Digital Signal Processor |
| SAA7709/N107 | 制造商:PHILIPS-SEMI 功能描述: |
| SAA7709H/N103 | 功能描述:音頻 DSP DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAA7709H/N103,518 | 功能描述:音頻 DSP DIRAC-2 RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAA7709H/N103,557 | 功能描述:音頻 DSP DIGITAL SIGNAL RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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