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參數(shù)資料
| 型號： | SAA7707H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Shaft; Style: 1 - light; Applicable Model: LE-P / LEL-W |
| 中文描述： | 0-BIT, 36.86 MHz, OTHER DSP, PQFP80 |
| 封裝： | 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80 |
| 文件頁數(shù)： | 17/48頁 |
| 文件大?。?/td> | 244K |
| 代理商： | SAA7707H |
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1997 May 30
17
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
9
ANALOG OUTPUTS
9.1
Digital-to-analog converters
Each of the four low-noise high dynamic range DACs
consists of a 15-bit signed magnitude DAC with current
output, followed by a buffer operational amplifier.
The five higher bits (bits 10 to 14) are used to control the
total coarse current ratio of the 32 coarse current sources
via a thermometer decoder. The nine lower bits
(bits 1 to 9) are derived from a 512 transistor matrix, which
acts as a passive 9-bit current divider for one of the coarse
currents. The MSB (bit 15) is used as a sign bit for the
signed magnitude converter and controls the direction of
the total output current. A separate converter is used for
each of the four audio output channels. The value of each
coarse current is adjusted by the current through the
external resistor connected to pin 13 (I
ref(int)
).
Each converter output is connected to the inverting input
of one of the four internal CMOS operational amplifiers.
The non-inverting input of this operational amplifier is
connected to the internal reference voltage. Together with
an external resistor, the current-to-audio output voltage
conversion is achieved.
9.2
Upsample filter
To reduce spectral components above the audio band, a
fixed 4 times oversampling and interpolating 18-bit digital
IIR filter is used. It is realized as a bit serial design and
consists of two consecutive filters. The data path in these
filters is 22 bits, to prevent overflow and to maintain a
theoretical signal-to-noise ratio greater than 105 dB.
The filters give an attenuation of at least 29 dB. The filter
is followed by a 5 bit 1st-order noise shaper, to expand the
dynamic range to more than 105 dB.
The band around multiples of the sample frequency of the
DAC (4f
as
) is not affected by the digital filter. A capacitor
can be added in parallel with the output resistor at the DAC
output to further attenuate this out-of-band noise to an
acceptable level.
The overall frequency spectrum at the DAC audio output
without external capacitor/low-pass filter for the audio
sampling frequencies (f
as
) of 38 kHz is illustrated in Fig.8.
The detailed spectrum around f
as
is illustrated in Fig.9 for
an f
as
of 38 kHz, 44.1 kHz and 48 kHz. The pass-band
bandwidth (at
3 dB) is
1
2
f
as
.
The word clock for the upsample filter (4f
as
) is derived from
the audio source timing. If the internal audio source is
selected, the sample frequency is fixed at 38 kHz.
For external digital sources (DCC and CD), a sample
frequency from 32 to 48 kHz is possible. The sample
frequency is automatically adjusted to the I
2
S-bus input by
dividing the external bit clock. This clock is normally
present in a DCC CD application. An internal digital PLL
divides this clock with the integer factor needed to obtain
the 4f
as
word clock. Master synchronization of this divided
clock signal is obtained with a reset of the divider on the
Word Select signal (trailing edge) of the I
2
S-bus.
In the application, the I
2
S-bus signal from the external
source should fulfil the following requirements:
There is a continuous (is part of the basic I
2
S-bus
specification) n
×
4f
as
(4
<
n
<
128) I
2
S-bus bit clock or
If the I
2
S-bus bit clock is not continuous, another n
×
4f
as
(4
<
n
<
128) continuous clock signal has to be
connected to the EXCLK pin (pin 40). The divide
external clock mode has to be selected using the input
selector control register.
The range of the internal 7-stage programmable divider of
the PLL, to obtain 4f
as
, is large enough to handle 16-bit
I
2
S-bus signals as well as master clocks up to 22 MHz
from digital sources (CD, DCC, R-DAT and EBU interface)
without any clock regeneration.
The PLL is used in a free-running mode to ensure that jitter
on the I
2
S-bus signals (due to asynchronous clocking of
the I
2
S-bus signals by the DSP core) will not influence the
total harmonic distortion of the audio signal on the analog
DAC part. This will, however, only operate if there is no
jitter on the bit clock or when a crystal clock is used.
9.3
Volume control
The total volume control has a dynamic range of more than
100 dB. With the signed magnitude noise-shaped 15-bit
DAC and the internal 18 bit registers of the DSP core, a
useful digital volume control range of 100 dB is possible by
calculating the corresponding coefficients. The step size is
freely programmable and an additional analog volume
control is not needed in this design. The signal-to-noise
ratio of the audio output, at full-scale, is determined by the
total 15 bits of the converter.
The noise at low outputs is fully determined by the noise
performance of the DAC. Since it is a signed magnitude
type, the noise at digital silence is also low.
The disadvantage is that the total THD is higher than
conventional DACs. The typical signal and noise levels as
a function of the output level and the typical signal-to-noise
plus THD as a function of the output level are illustrated in
Fig.10.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7708H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Car Radio Digital Signal Processor |
| SAA7709/N107 | 制造商:PHILIPS-SEMI 功能描述: |
| SAA7709H/N103 | 功能描述:音頻 DSP DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAA7709H/N103,518 | 功能描述:音頻 DSP DIRAC-2 RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAA7709H/N103,557 | 功能描述:音頻 DSP DIGITAL SIGNAL RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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