參數(shù)資料
型號: SAA7707H
廠商: NXP SEMICONDUCTORS
元件分類: 數(shù)字信號處理
英文描述: Shaft; Style: 1 - light; Applicable Model: LE-P / LEL-W
中文描述: 0-BIT, 36.86 MHz, OTHER DSP, PQFP80
封裝: 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80
文件頁數(shù): 10/48頁
文件大?。?/td> 244K
代理商: SAA7707H
1997 May 30
10
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
8
FUNCTIONAL DESCRIPTION
8.1
Signal path for level information
An FM and AM level input is implemented for FM weak
signal processing [for AM, FM and RDS search purposes
(absolute level and multi-path)]. A DC input signal is
converted by a bitstream 1st-order Sigma-Delta
analog-to-digital converter and then filtered by a
decimation filter.
The input signal has to be obtained from the radio part.
Two different circuits for AM and FM reception are
possible:
1.
A circuit with two separate input signals, one for FM
level and one for AM level
2.
A combined circuit with AM and FM level information
on the FM level input. The AM level input can then be
connected to another signal, which can be converted
in the non-radio mode.
The input is selected via the input selector control register.
The input signal for level control must be in the range of
0 to 5 V. The 11-bit level ADC converts this input voltage
in steps with a resolution better than 10 mV over the 5 V
range. The tolerance on the gain is less than 10%.
The MSB is always logic 0, to represent a positive level.
The decimation filter reduces the bandwidth of the
incoming signal to a frequency range of 0 to 29 kHz, with
a resulting sampling frequency (f
s
) of 76 kHz.
The response curve is illustrated in Fig.3.
The level information is sub-sampled by the DSP core to
obtain a field strength and a multi-path indication.
These values are stored in the coefficient or data RAM.
They can be read and used in other microcontroller
programs via the I
2
C-bus.
8.2
Level ADC switch mode integrator (pin CINT)
The level ADC has an internal current summation point of
the input level and the switch capacitor DAC. When used
as an integrator, an external capacitor of 1000 pF should
be connected between this pin and the analog ground at
pin V
SSA1
. The summation voltage is used as an input for
the analog-to-digital comparator level.
8.3
Internal ground reference for the level ADC
(pin V
DACNL
)
This pin serves as the internal ground reference for the
switch capacitor DAC and the level ADC and has to be
connected to the analog ground (pin V
SSA1
).
Fig.3 Frequency response of the level ADC and decimation filter.
handbook, full pagewidth
(dB)
0
80
60
0
20
10
30
40
50
60
70
f (kHz)
MBH164
10
20
30
50
40
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