參數(shù)資料
型號(hào)： SAA7199
廠商： NXP Semiconductors N.V.
英文描述： Digital Video Encoder DENC GENLOCK-capable
中文描述： 數(shù)字視頻編碼器DENC同步鎖相能力
文件頁(yè)數(shù)： 17/40頁(yè)
文件大小： 188K
代理商： SAA7199
1996 Sep 27
17
Philips Semiconductors
Product specification
Digital Video Encoder (DENC)
GENLOCK-capable
SAA7199B
Modes of the SAA7199B
Table 18
The four different modes of the SAA7199B
R
ELATIONSHIP BETWEEN HORIZONTAL FREQUENCY AND COLOUR SUBCARRIER FREQUENCY IN NON
-GENLOCK
MODE
1.
Internal subcarrier frequency with n = integer
PAL: f
SC
= f
H
(n/4 + 1/625) respectively f
H
(n/4 + 1/525)
NTSC: f
SC
= f
H
(n/2)
Necessary conditions: non-GENLOCK mode; RTCE = 0, FSCO = 00H; phase coupling of the two frequencies is
given by a definite phase reset every 8th field at PAL (4th field at NTSC).
FSCO
≠
00H adjusts the subcarrier frequency, phase reset is disabled and phase between f
SC
and f
H
is not constant.
External subcarrier frequency
f
SC
is given by RTCI real time input from a digital colour decoder
Necessary conditions: Slave mode; RTCE = 1, RTSC = 1. The 8th respectively 4th field reset is enabled at
FSCO = 00H (disabled at FSCO
≠
00H). The subcarrier frequency is not influenced by FSCO bits, but is given by
real time increment.
External HPLL increment
f
SC
is calculated by RTCI real time input signal from a digital colour decoder. The frequency of f
SC
depends on the
absolute crystal frequency value used by the digital colour decoder.
Necessary conditions: Slave mode; RTCE = 1, RTSC = 0. The 8th respectively 4th field reset is enabled at
FSCO = 00H (disabled at FSCO
≠
00H). The subcarrier frequency is influenced by FSCO bits.
2.
3.
The absolute phase relationship between sync and subcarrier (colour burst output) can be influenced in all three events
by CHPS7 to CHPS0 register byte (index 0C).
MODE
DESCRIPTION
Stand alone
The SAA7199B receives a line-locked clock CLKIN and generates CSYN or HSN/VSN output
signals, which trigger the RGB or the YUV source signal to provide data and composite blanking CB.
The SAA7199B receives the line-locked clock CLKIN, CSYN or HSN/VSN, CB and data from an
RGB or YUV source. The sync inputs are edge-sensitive; their minimum active length is 1 PIXCLK.
A real time control signal RTCI is received from a digital colour decoder as an option.
Horizontal and vertical sync plus colour are locked on a received CVBS reference signal. The CVBS
reference signal also generates a line-locked clock by the SAA7197 clock generator. Auxiliary
signals HCL and HSY plus CSYN or HSN/VSN are generated to trigger the RGB or the YUV source
providing data and composite blanking CB.
Similar to stand alone mode, but the contents of the test registers TRER, TREG and TREB consists
of data to be encoded. VSN/CSYN and HSN outputs are in 3-state condition.
Slave
GENLOCK
Test
相關(guān)PDF資料
PDF描述
SAA7199BWP Digital Video Encoder DENC GENLOCK-capable
SAA7199B ; Capacitance:1uF; Capacitance Tolerance:+/- 10 %; Working Voltage, DC:100V; Terminal Type:Axial Leaded; Series:430P; Dielectric Material:Metalized Polyester; Mounting Type:Through Hole; Operating Temp. Max:85 C
SAA7205 MPEG-2 systems demultiplexer
SAA7205H MPEG-2 systems demultiplexer
SAA7206 DVB compliant descrambler
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA7199B 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder DENC GENLOCK-capable
SAA7199BWP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder DENC GENLOCK-capable
SAA7201 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated MPEG2 AVG decoder
SAA7201H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated MPEG2 AVG decoder
SAA7205 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 systems demultiplexer
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