參數(shù)資料
型號(hào)： SAA7199
廠商： NXP Semiconductors N.V.
英文描述： Digital Video Encoder DENC GENLOCK-capable
中文描述： 數(shù)字視頻編碼器DENC同步鎖相能力
文件頁(yè)數(shù)： 25/40頁(yè)
文件大?。?/td> 188K
代理商： SAA7199
1996 Sep 27
25
Philips Semiconductors
Product specification
Digital Video Encoder (DENC)
GENLOCK-capable
SAA7199B
Reset
Prior to a reset all outputs are undefined. RESET = LOW
sets the circuit into the slave mode.
MOD1 bit = 1, MOD0-bit = 0. All other control register bits
are set to zero. The outputs CSYN/VSN, HSN, SLT, HSY
and HCL are automatically set to a high impedance
state.The I
2
C-bus interface is set to a slave receiver.
The D7 to D0 pins of the MPU interface are inputs during
RESET = LOW. As the circuit requires an external clock
signal on pin CLKIN in slave mode, the clock select signal
CLKSEL (pin 50) must be LOW during RESET = LOW
(pin 54). The LOW time of RESET is at least 50 pixel clock
periods long.
Disable chip
All analog outputs are set to zero by DD-bit = 1 (index 08);
while the outputs CSYN/VSN, HSN, HCL, HSY and SLT
are set to a high impedance state. The internal clock is
divided-by-4 at DD-bit = 1. The circuit can be disabled for
any reason and it must be disabled when CLKIN exceeds
32 MHz. After setting DD-bit = 1, the CLKIN input signal
can be set to a frequency of <60 MHz (modification of
control registers and RAM tables is not certain).
To re-enable the circuit, CLKIN must be set to a frequency
<32 MHz, a hardware reset is then required to set DD-bit
to zero.
Fig.10 Horizontal timing.
(1) t
Rint
is the pipeline delay of the RAM interface adjustable from
5 to +58 pixel clocks (PIXCLK).
(2)
t = 125
×
PIXCLK at 12.27 MHz
t = 163
×
PIXCLK at 14.75 MHz
t = 134
×
PIXCLK at 13.50 MHz in 50 Hz mode
t = 122
×
PIXCLK at 13.50 MHz in 60 Hz mode.
(3) t
ofs
is the propagation delay of external GENLOCK line adjustable from
17 to +46 pixel clocks.
handbook, full pagewidth
MEH345-1
CVBS input signal;
GENLOCK only
tREF2
tREF1
tRint
(1)
t
(2)
tenc
tofs
(3)
HSN output signal
CB input signal
PDn(7 to 0)
digital input data
CVBS output signal
active video
0 to 640/720/780
PIXCLK
相關(guān)PDF資料
PDF描述
SAA7199BWP Digital Video Encoder DENC GENLOCK-capable
SAA7199B ; Capacitance:1uF; Capacitance Tolerance:+/- 10 %; Working Voltage, DC:100V; Terminal Type:Axial Leaded; Series:430P; Dielectric Material:Metalized Polyester; Mounting Type:Through Hole; Operating Temp. Max:85 C
SAA7205 MPEG-2 systems demultiplexer
SAA7205H MPEG-2 systems demultiplexer
SAA7206 DVB compliant descrambler
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA7199B 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder DENC GENLOCK-capable
SAA7199BWP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder DENC GENLOCK-capable
SAA7201 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated MPEG2 AVG decoder
SAA7201H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated MPEG2 AVG decoder
SAA7205 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 systems demultiplexer
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