
1996 Sep 27
5
Philips Semiconductors
Product specification
Digital Video Encoder (DENC)
GENLOCK-capable
SAA7199B
A1
R/W
CS
D0
D1
D2
D3
V
DDD3
V
SSD3
D4
D5
D6
D7
SDA
SCL
CLKIN
CLKSEL
PIXCLK
CLKO
TP
RESET
LLC
CREF
GPSW/RTCI
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
subaddress bit A1 input for microcontroller access (Table 3)
read/write not input signal from microcontroller
chip select input for parallel interface; active LOW
bidirectional port from/to microcontroller; bit D0
bidirectional port from/to microcontroller; bit D1
bidirectional port from/to microcontroller; bit D2
bidirectional port from/to microcontroller; bit D3
digital supply 3 (5 V)
digital ground 3
bidirectional port from/to microcontroller; bit D4
bidirectional port from/to microcontroller; bit D5
bidirectional port from/to microcontroller; bit D6
bidirectional port from/to microcontroller; bit D7
I
2
C-bus data input/output
I
2
C-bus clock input
external clock signal input (maximum frequency 60 MHz)
clock source select input
CLKO/2 or conditionally CLKO output signal
selected clock output signal (LLC or CLKIN)
test pin; connected to ground
reset input; active LOW
line-locked clock input signal from external clock generation circuit (CGC)
clock qualifier input of external CGC
general purpose switch output (set via I
2
C-bus or MPU-bus); real time control input, defined
by I
2
C or MPU programming
GENLOCK output flag (3-state): HIGH = sync lost in GENLOCK mode; LOW = otherwise
crystal oscillator input (26.8 or 24.576 MHz)
crystal oscillator output
line frequency control output signal for external CGC
reference voltage LOW of DACs (resistor chains)
reference voltage HIGH of DACs (resistor chains)
analog supply 4 for resistor chains of the DACs (5 V)
chrominance analog output signal
analog supply 1 for output buffer amplifier of DAC1 (5 V)
luminance analog output signal
analog ground (0 V)
CVBS analog output signal
analog supply 2 for output buffer amplifier of DAC2 (5 V)
current input for analog output buffers
analog supply 3 for output buffer amplifier of DAC3 (5 V)
key input signal to insert CVBS input signal into encoded CVBS output signal; active HIGH
SLT
XTALI
XTALO
LFCO
V
refL
V
refH
V
DDA4
C
V
DDA1
Y
V
SSA
CVBS
V
DDA2
CUR
V
DDA3
KEY
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
SYMBOL
PIN
DESCRIPTION