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參數(shù)資料
| 型號： | SAA7151B |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Digital multistandard colour decoder with SCART interface DMSD2-SCART |
| 中文描述： | COLOR SIGNAL DECODER, PQCC68 |
| 封裝： | PLASTIC, MO-047AC, SOT-188-2, LCC-68 |
| 文件頁數(shù)： | 4/49頁 |
| 文件大?。?/td> | 311K |
| 代理商： | SAA7151B |
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April 1993
4
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
PINNING
SYMBOL
PIN
DESCRIPTION
SP
AP
RESN
CREF
V
DD1
CUV0
CUV1
CUV2
CUV3
CUV4
CUV5
CUV6
CUV7
CVBS0
CVBS1
CVBS2
CVBS3
V
DD2
V
SS1
CVBS4
CVBS5
CVBS6
CVBS7
GPSW1
GPSW2
HCL
LL27
V
DD3
HSY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
connected to ground (shift pin for testing)
connected to ground (action pin for testing)
reset, active-LOW
clock reference, sync from external to ensure in-phase signals on the Y-, CUV- and YUV-bus
+
5 V supply input 1
chrominance input data bits CUV7 to CUV0 (digitized chrominance signals in two’s complement
format from a S-Video source (S-VHS, Hi8) or time-multiplexed colour-difference signals from a
YUV(RGB) source or both in combination)
CVBS lower input data bits CVBS3 to CVBS0
(CVBS with luminance, chrominance and all sync information in two’s complement format)
+
5 V supply input 2
ground 1 (0 V)
CVBS upper input data bits CVBS7 to CVBS4
(CVBS with luminance, chrominance and all sync information in two’s complement format)
status bit output FSST0 or port 1 output for general purpose (programmable by subaddress 0C)
status bit output FSST1 or port 2 output for general purpose (programmable by subaddress 0C)
black level clamp pulse output (begin and stop programmable), e.g. for TDA8708A (ADC)
line-locked system clock input signal (27 MHz)
+
5 V supply input 3
hor. sync pulse reference output (begin and stop programmable), e.g. for gain adj.TDA8708A
(ADC)
vertical sync output signal (Fig.11)
horizontal sync output signal (Fig.16; start point programmable)
real time control output; serial increments of HPLL and FSCPLL and status PAL or SECAM
sequence (Fig.10)
24.576 MHz clock output (open-circuit for use with external oscillator)
24.576 MHz connection for crystal or external oscillator (TTL compatible squarewave)
analog ground
line frequency control output signal, multiple of horizontal frequency (nominal 6.75 MHz)
+
5 V supply input for analog part
ground 2 (0 V)
VS
HS
RTCO
30
31
32
XTAL
XTALI
V
SSA
LFCO
V
DDA
V
SS2
33
34
35
36
37
38
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