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參數(shù)資料
| 型號： | SAA7151B |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Digital multistandard colour decoder with SCART interface DMSD2-SCART |
| 中文描述： | COLOR SIGNAL DECODER, PQCC68 |
| 封裝： | PLASTIC, MO-047AC, SOT-188-2, LCC-68 |
| 文件頁數(shù)： | 38/49頁 |
| 文件大?。?/td> | 311K |
| 代理商： | SAA7151B |
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April 1993
38
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
Notes
1.
2.
an internal sign-bit D8 set to HIGH indicates that all values are always negative
H-PLL does not operate in this condition; the system clock frequency is set to a value fixed by the last update and is
within
±
7.1 % of the nominal frequency.
OEDY
“12”
OEDC
Enable Y signals on YUV-bus:
0 = output high-impedance; 1 = output active
(dependent on FEIN)
Enable UV signals on YUV-bus:
0 = output high-impedance; 1 = output active
(dependent on FEIN)
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-
-
-
-
-
-
-
VNOI1, VNOI0
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-
-
-
-
-
-
-
-
-
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-
-
-
-
-
-
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Vertical noise reduction mode:
VNOI1
0
0
1
1
VNOI0
0
1
0
1
mode
normal
searching
free-running
bypassed
BFON
BOFL2 to BOFL0
Bottom flutter compensation switching: 0 = off; 1 = on (controlled by BOFL-bit)
Bottom flutter compensation
BOFL2
BOFL1
BOFL0
0
0
1
1
1
1
The bottom flutter circuit is able to compensate for horizontal phase jump of up to
±
16
μ
s.
Note: The bottom flutter gate is active at
- HPLL is locked
- HPLL in VTR mode
- the vertical noise limiter (VNL)
is in the VTR mode
- gating is switched by
BFON-bit = 1 (subaddress 12)
Gate 2
Gate 1
HPLL function
0
1
0
1
1
unused
start at line number
297 for PAL (247 for NTSC; active to end of field)
298 for PAL (248 for NTSC; active to end of field)
.
.
303 for PAL (253 for NTSC; active to end of field)
304 for PAL (254 for NTSC; active to end of field)
0
0
1
0
1
0
0
0
1
normal
disabled
double speed
vertical
pulse
gate 2
gate 1
programmable by BOFL(2-0)
000
111
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