參數(shù)資料
型號(hào)： SAA7151B
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 顏色信號(hào)轉(zhuǎn)換
英文描述： Digital multistandard colour decoder with SCART interface DMSD2-SCART
中文描述： COLOR SIGNAL DECODER, PQCC68
封裝： PLASTIC, MO-047AC, SOT-188-2, LCC-68
文件頁(yè)數(shù)： 36/49頁(yè)
文件大?。?/td> 311K
代理商： SAA7151B
April 1993
36
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
COLO
“0D”
CHSB
GPSW0
SUVI
SXCR
-
-
-
-
-
-
-
-
FDSL2 to FDSL0
Colour-on bit:
0 = colour-killer automatically enabled;
1 = forced colour-on.
0 = two’s complement; 1 = straightly binary
0 = LOW; 1 = HIGH
0 = U and V positive; 1 = U and V negative
0 = off; 1 = on
Chrominance (UV) output code:
General purpose port output (pin 63):
SECAM UV output signal polarity:
SECAM cross-colour reduction:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Fast switching delay adjustment in 37 ns steps:
FDSL2
FDSL1
FDSL0
delay
0
0
0
0
1
1
111 ns
1
1
1
1
1
1
37 ns
Set CCIR mode: 0 = digital TV mode (DTV); 1 = CCIR mode
0
0
1
0
1
0
0
37 ns
74 ns
0
0
1
0
1
0
148 ns (negative delay)
111 ns
74 ns
CCIR
“0E”
COFF
OEHS
Set colour off: 0 = colour on; 1 = colour off
Enable horizontal sync outputs HS and HREF:
0 = output high-impedance;
1 = HS and HREF enabled
0 = output high-impedance; 1 = VS enabled
1 = first pixel after U/V signal has changed;
0 = second pixel (free of crosstalk signals)
0 = chrominance signal from CVBS or CUV input
and controlled by BYPS (subaddress 06);
1 = S-Video mode; chrominance signal from CUV input
OEVS
UVSS
Enable vertical sync output VS:
Select UV pixel sample:
CHRS
S-Video input mode:
-
-
-
-
-
-
-
-
CDMO, CDPO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Chrominance delay:
CDMO
CDPO
0
1
0
1
Automatic field detection:
0 = field selection by FSEL-bit;
1 = automatic field detection
Field select (AUFD-bit = 0):
0 = 50 Hz (625 lines);
1 = 60 Hz (525 lines)
Horizontal PLL:
0 = PLL closed; 1 = PLL open, horizontal frequency fixed
Sync and clamping pulse enable:
0
X
no delay
37 ns (negative delay)
+
37 ns
AUFD
“0F”
FSEL
HPLL
SCEN
0 = HCL and HSY outputs HIGH (pins 26 and
29);
1 = HCL and HSY outputs active.
0 = TV mode (slow time constant);
1 = VTR mode (fast time constant).
0 = inverted; 1 = not inverted
0 = not inverted; 1 = inverted
0 = off; 1 = on
VTRC
VTR/TV mode select:
MUIV
FSIV
WIND
MUXC signal invertion:
Fast switch input signal inversion:
Narrow fast switch window:
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