參數(shù)資料
型號(hào)： SAA7151B
廠商： NXP SEMICONDUCTORS
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Digital multistandard colour decoder with SCART interface DMSD2-SCART
中文描述： COLOR SIGNAL DECODER, PQCC68
封裝： PLASTIC, MO-047AC, SOT-188-2, LCC-68
文件頁(yè)數(shù)： 8/49頁(yè)
文件大小： 311K
代理商： SAA7151B
April 1993
8
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
For matrixed RGB signals - the full screen SCART mode
and the fast insertion mode (blanking/switching) are
selectable. The chrominance stop filter is automatically
bypassed in full screen SCART mode.
Full screen RGB mode (SCART):
The CUV digital input signal (7-0) consists of
time-multiplexed samples for U and V. An offset correction
for both signals is applied to correct external clamping
errors. An internal timing correction compensates for slight
differences in timing during sampling. The U and V signals
are delay-compensated and fed to the output formatter.
The format 4:2:2 or 4:1:1 is generated by a switchable
filter.
The control signals for the front end (Figures 3 and 20)
MUXC, status bits FSST1, FSST0 (outputs GPSW2,
GPSW1) and FSO are generated by the SAA7151B.
Table 1
SCART interface control (Fig.3)
MODE
CONNECTION
chroma
output of
TDA8446
to TDA8709A
TDA8709A
luminance
fast switch
TDA8446
input
selector (via
I
2
C-bus)
TDA8540
FSO GPSW 2
GPSW 1 MUXC
selected
input
CUV
(7-0)
RGB
only
Y/C or
CVBS
only
Fast
switch
0
0
0
0
0
0
0
1
high-Z
VIN2
U/V
sync (RGB)
sync (RGB)
0
0
0
0
1
1
0
1
C
VIN1
C
Y (Y/C) or CVBS
Y (Y/C) or
CVBS
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
C
VIN2
0.5(C
+
U)/
0.5(C
+
V)
Y (Y/C) or CVBS
Y (Y/C) or
CVBS
not used
RGB
only
high-Z
VIN2
U/V
Y (RGB)
sync (RGB)
not used
Fast
switch
C
VIN2
0.5(C
+
U)/
0.5(C
+
V)
Y (RGB)
Y (Y/C) or
CVBS
not used
Fast insertion mode:
Fast insertion is applied by FSI pulse to ensure correct
timing. The RGB source signal is matrixed into UV and
inserted into the CVBS or Y/C source signal after two field
periods if FSI pulses are received. The output FSO is set
to HIGH during a determined insertion window (screen
plain minus 6 % of horizontal and vertical deflection).
Switch over depends on the phase of FSI in relation to the
valid pixel sequence depending on the phase-different
weighting factors. They are applied to the original and the
inserted UV data (Figures 6 and 7)
The control signals for the front end (Table 1) MUXC, FSO,
status bits FSST1 and FSST0 (outputs GPSW2 and
GPSW1) are generated by the SAA7151B.
The amplitude of chrominance and colour-difference
signals are scaled down by factor 2 to avoid overloading of
the chrominance analog-to-digital converter. The
amplitudes are reduced in the TDA8446 by signals on lines
GPSW2 and GPSW1.
相關(guān)PDF資料
PDF描述
SAA7157 Clock signal generator circuit for digital TV systems SCGC
SAA7157T Clock signal generator circuit for digital TV systems SCGC
SAA7158 Back END IC
SAA7158WP Back END IC
SAA7165 Digital Video Encoder EURO-DENC2
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA7152 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Comb Filter DCF
SAA7154E/V2/G,557 制造商:NXP Semiconductors 功能描述:
SAA7154H/V2,557 制造商:NXP Semiconductors 功能描述:
SAA7157 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Clock signal generator circuit for digital TV systems SCGC
SAA7157T 制造商:NXP Semiconductors 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*