
2003 Dec 09
32
Philips Semiconductors
Product specification
Digital video encoder
SAA7128AH; SAA7129AH
Table 61
Subaddress 71H
Table 62
Subaddress 72H
Table 63
Subaddress 73H
Table 64
Subaddress 74H
Table 65
Subaddress 75H
BIT
SYMBOL
DESCRIPTION
7 to 0
RCV2E[7:0]
These are the 8 LSBs of the 11-bit code that determines the end of the output signal
on the RCV2 pin; the 3 MSBs of the 11-bit code are held at subaddress 72H; see
Table 62. Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed. Leading
sync slope at CVBS output coincides with trailing slope of RCV2 out at RCV2E = 49H.
BIT
SYMBOL
RCV2E10
RCV2E9
RCV2E8
RCV2S10
RCV2S9
RCV2S8
DESCRIPTION
7
6
5
4
3
2
1
0
This bit is reserved and must be set to a logic 0.
These are the 3 MSBs of end of output signal code; see Table 61.
This bit is reserved and must be set to a logic 0.
These are the 3 MSBs of start of output signal code; see Table 60.
BIT
SYMBOL
DESCRIPTION
7 to 0
TTXHS[7:0]
Start of signal on pin TTXRQ; see Fig.23.
PAL: TTXHS[7:0] = 42H
NTSC: TTXHS[7:0] = 54H
BIT
SYMBOL
DESCRIPTION
7 to 0
TTXHD[7:0]
Indicates the delay in clock cycles between rising edge of TTXRQ output and valid
data at pin TTX.
minimum value: TTXHD[7:0] = 2
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
CSYNCA4
CSYNCA3
CSYNCA2
CSYNCA1
CSYNCA0
VS_S2
Advanced composite sync against RGB output from 0 to 31 LLC clock periods.
Vertical sync shift between RCV1 and RCV2 (switched to output); in master mode it is
possible to shift Hsync (RCV2; CBLF = 0) against Vsync (RCV1; SRCV1 = 00).
standard value: VS_S[2:0] = 3
1
0
VS_S1
VS_S0