參數(shù)資料
型號(hào): SAA7128A
廠商: NXP Semiconductors N.V.
英文描述: Digital video encoder
中文描述: 數(shù)字視頻編碼器
文件頁(yè)數(shù): 26/55頁(yè)
文件大?。?/td> 262K
代理商: SAA7128A
2003 Dec 09
26
Philips Semiconductors
Product specification
Digital video encoder
SAA7128AH; SAA7129AH
Table 42
Subaddress 61H
Table 43
Subaddress 62H
BIT
SYMBOL
DESCRIPTION
7
DOWNB
0 = DACs for R, G and B in normal operational mode
1 = DACs for R, G and B forced to lowest output voltage; default state after reset
0 = DACs for CVBS, Y and C in normal operational mode; default state after reset
1 = DACs for CVBS, Y and C forced to lowest output voltage
0 = PAL switch phase is nominal; default state after reset
1 = PAL switch phase is inverted compared to nominal if RTC is enabled; see Table 43
0 = luminance gain for white
black 100 IRE; default state after reset
1 = luminance gain for white
black 92.5 IRE including 7.5 IRE set-up of black
0 = no SECAM encoding; default state after reset
1 = SECAM encoding activated; bit PAL has to be set to logic 0
0 = enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 8 and 9)
1 = standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 8 and 9); default state after reset
0 = NTSC encoding (non-alternating V component)
1 = PAL encoding (alternating V component); default state after reset
0 = 864 total pixel clocks per line; default state after reset
1 = 858 total pixel clocks per line
6
DOWNA
5
INPI
4
YGS
3
SECAM
2
SCBW
1
PAL
0
FISE
BIT
SYMBOL
DESCRIPTION
7
RTCE
0 = no real-time control of generated subcarrier frequency; default state after reset
1 = real-time control of generated subcarrier frequency through SAA7151B or
SAA7111; for timing see Fig.22
amplitude of colour burst; input representation in accordance with “ITU-R BT.601”
see Table 44
6 to 0
BSTA[6:0]
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