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參數(shù)資料
| 型號： | SAA7128A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital video encoder |
| 中文描述： | 數(shù)字視頻編碼器 |
| 文件頁數(shù)： | 20/55頁 |
| 文件大?。?/td> | 262K |
| 代理商： | SAA7128A |
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2003 Dec 09
20
Philips Semiconductors
Product specification
Digital video encoder
SAA7128AH; SAA7129AH
Table 16
Subaddress 3AH
Table 17
Subaddresses 42H to 44H and 48H to 4AH
Table 18
Subaddresses 45H to 47H and 4BH to 4DH
Table 19
Subaddress 4EH
BIT
SYMBOL
DESCRIPTION
7
CBENB
0 = data from input ports is encoded; default state after reset
1 = colour bar with fixed colours is encoded
These 2 bits are reserved; each must be set to a logic 0.
6
5
4
SYMP
0 = horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default
state after reset
1 = horizontal and vertical trigger is decoded out of “ITU-R BT.656”compatible data at
MPEG port
0 = YC
B
C
R
-to-RGB dematrix is active; default state after reset
1 = YC
B
C
R
-to-RGB dematrix is bypassed
0 = CVBS output signal is switched to CVBS DAC; default state after reset
1 = advanced composite sync is switched to CVBS DAC
0 = input data is twos complement from MPEG port fader input
1 = input data is straight binary from MPEG port fader input; default state after reset
0 = input data is twos complement from Video port fader input
1 = input data is straight binary from Video port fader input; default state after reset
3
DEMOFF
2
CSYNC
1
MP2C
0
VP2C
ADDRESS
BYTE
DESCRIPTION
42H
48H
43H
49H
44H
4AH
KEY1LU
KEY1UU
KEY1LV
KEY1UV
KEY1LY
KEY1UY
Key colour 1 lower and upper limits for U, V and Y. If MPEG input signal is within the
limits of key colour 1 the incoming signals at the Video port and MPEG port are added
together according to the equation:
FADE1
×
video signal + (1
FADE1)
×
MPEG signal
Default value of all bytes after reset = 80H.
ADDRESS
BYTE
DESCRIPTION
45H
4BH
46H
4CH
47H
4DH
KEY2LU
KEY2UU
KEY2LV
KEY2UV
KEY2LY
KEY2UY
Key colour 2 lower and upper limits for U, V and Y. If MPEG input signal is within the
limits of key colour 2 the incoming signals at the Video port and MPEG port are added
together according to the equation:
FADE2
×
video signal + (1
FADE2)
×
LUT values
Default value of all bytes after reset = 80H.
BIT
SYMBOL
FADE1[5:0]
DESCRIPTION
7 to 6
5 to 0
These 2 bits are reserved; each must be set to logic 0.
These 6 bits form factor FADE1 which determines the ratio between the MPEG and
video input signal in the resulting video data stream if the key colour 1 is detected in the
MPEG input signal.
FADE1 = 00H: 100% MPEG, 0% video
FADE1 = 3FH: 100% video, 0% MPEG; this is the default value after reset
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7128AH | Digital video encoder |
| SAA7129AH | Digital video encoder |
| SAA7129AH | Digital video encoder |
| SAA7128 | Digital video encoder |
| SAA7128H | Digital video encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7128AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder |
| SAA7128H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder |
| SAA7129 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder |
| SAA7129/DENC29A | 制造商:NXP Semiconductors 功能描述: |
| SAA7129AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder |
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