
2003 Dec 09
22
Philips Semiconductors
Product specification
Digital video encoder
SAA7128AH; SAA7129AH
Table 25
Subaddress 54H
Table 26
Subaddress 55H
Table 27
Subaddress 56H
Table 28
Subaddress 57H
Table 29
Subaddress 58H
Table 30
Subaddress 59H
BIT
SYMBOL
DESCRIPTION
7
VPSEN
0 = video programming system data insertion is disabled; default state after reset
1 = video programming system data insertion in line 16 is enabled
This bit is not used and should be set to logic 0.
0 = encoder path is fed with MP
B
input data; fader is bypassed; default state after reset
1 = encoder path is fed with output signal of fader; see Section 7.1
0 = RGB path is fed with MP
B
input data; fader is bypassed; default state after reset
1 = RGB path is fed with output signal of fader; see Section 7.1
0 = not supported in current version; do not use
1 = recommended value; default state after reset
0 = not supported in current version; do not use
1 = recommended value; default state after reset
0 = MP
B
data is sampled on the rising clock edge; default state after reset
1 = MP
B
data is sampled on the falling clock edge
0 = MP
A
data is sampled on the rising clock edge; default state after reset
1 = MP
A
data is sampled on the falling clock edge
6
5
ENCIN
4
RGBIN
3
DELIN
2
VPSEL
1
EDGE2
0
EDGE1
BIT
SYMBOL
DESCRIPTION
7 to 0
VPS5[7:0]
Fifth byte of video programming system data in line 16; LSB first.
BIT
SYMBOL
DESCRIPTION
7 to 0
VPS11[7:0]
Eleventh byte of video programming system data in line 16; LSB first.
BIT
SYMBOL
DESCRIPTION
7 to 0
VPS12[7:0]
Twelfth byte of video programming system data in line 16; LSB first.
BIT
SYMBOL
DESCRIPTION
7 to 0
VPS13[7:0]
Thirteenth byte of video programming system data in line 16; LSB first.
BIT
SYMBOL
DESCRIPTION
7 to 0
VPS14[7:0]
Fourteenth byte of video programming system data in line 16; LSB first.