2001 May 30
76
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
The following deviations from “ITU 656 recommendation”
are implemented at the SAA7118s image port interface:
SAV and EAV codes are only present in those lines,
where data is to be transferred, i.e. active video lines, or
VBI raw samples, no codes for empty lines
There may be more or less than 720 pixels between
SAV and EAV
Data content and the number of clock cycles during
horizontal and vertical blanking is undefined, and may
not be constant
Data stream may be interleaved with not-valid data
codes, 00H, but SAV and EAV 4-byte codes are not
interleaved with not-valid data codes
There may be an irregular pattern of not-valid data, or
IDQ, and as a result, C
B
-Y-C
R
-Y is not in a fixed phase
to a regular clock divider
VBI raw sample streams are enveloped with
SAV and EAV, like normal video
Decoded VBI-data is transported as Ancillary (ANC)
data, two modes:
– direct decoded VBI-data bytes (8-bit) are directly
placed in the ANC data field, 00H and FFH codes
may appear in data block (violation to ITU-R BT.656)
– recoded VBI-data bytes (8-bit) directly placed in ANC
data field, 00H and FFH codes will be recoded to
even parity codes 03H and FCH to suppress invalid
ITU-R BT.656 codes.
There are no empty cycles in the ancillary code and its
data field. The data codes 00H and FFH are suppressed
(changed to 01H or FEH respectively) in the active video
stream, as well as in the VBI raw sample stream (VBI
pass-through). Optionally, the number range can be
further limited.
Table 32
Signals dedicated to the image port
Note
1.
Pin numbers for QFP160 in parenthesis.
SYMBOL
PIN
(1)
I/O
DESCRIPTION
BIT
IPD7 to
IPD0
K11, J13, J14,
H13,H14,H11,
G12 and G14
(92 to 94, 97 to
100 and 102)
M14 (84)
I/O I-port data
ICODE[93H[7]], ISWP[1:0]
85H[7:6] and IPE[1:0] 87H[1:0]
ICLK
I/O continuous reference clock at image port, can
be input or output, as output decoder LLC or
XCLK from X-port
O
data valid flag at image port, qualifier, with
programmable polarity;
secondary function: gated clock
O
horizontal reference output signal, copy of the
H-gate signal of the scaler, with programmable
polarity; alternative function: HRESET pulse
O
vertical reference output signal, copy of the
V-gate signal of the scaler, with programmable
polarity; alternative function: VRESET pulse
O
general purpose output signal for I-port
ICKS[1:0] 80H[1:0] and IPE[1:0]
87H[1:0]
IDQ
L13 (85)
ICKS2[80H[2]], IDQP[85H[0]] and
IPE[1:0] 87H[1:0]
IGPH
K12 (91)
IDH[1:0] 84H[1:0], IRHP[85H[1]]
and IPE[1:0] 87H[1:0]
IGPV
K14 (90)
IDV[1:0] 84H[3:2], IRVP[85H[2]]
and IPE[1:0] 87H[1:0]
IGP1
K13 (89)
IDG12[86H[4]], IDG1[1:0] 84H[5:4],
IG1P[85H[3]] and IPE[1:0] 87H[1:0]
IDG02[86H[5]], IDG0[1:0] 84H[7:6],
IG0P[85H[4]] and IPE[1:0] 87H[1:0]
IPE[1:0] 87H[1:0]
IGP0
L14 (87)
O
general purpose output signal for I-port
ITRDY
ITRI
N12 (77)
L12 (86)
I
I
target ready input signals
port control, switches I-port into 3-state