2001 May 30
72
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
9.4.3
E
RASING CONDITIONS
The status flags are grouped into four 8-bit registers.
The interrupt flag will only be cleared on a read access to
the status register in which the signal is located which
causedtheinterrupt.Thisimpliesthatitissufficienttoclear
the interrupt by reading only those registers which have
been enabled by their corresponding masks.
Priority: If a new trigger condition occurs at the SAME time
(clock) on which a status is being read, the flag will NOT
be cleared.
9.5
Video expansion port (X-port)
The expansion port is intended for transporting video
streams image data from other digital video circuits such
as MPEG encoder/decoder and video phone codec, to the
image port (I-port).
The expansion port consists of two groups of signals/pins:
8-bit data, I/O, regularly components video Y-C
B
-C
R
4 : 2 : 2, i.e. C
B
-Y-C
R
-Y, byte serial, exceptionally raw
video samples (e.g. ADC test). In input mode the data
bus can be extended to 16-bit by pins HPD7 to HPD0.
Clock, synchronization and auxiliary signals,
accompanying the data stream, I/O.
As output, these are direct copies of the decoder signals.
The data transfers through the expansion port represent a
single D1 port, with half duplex mode. The SAV and EAV
codes may be inserted optionally for data input (controlled
by bit XCODE[92H[3]]). The input/output direction is
switched for complete fields only.
Table 27
Signals dedicated to the expansion port
Note
1.
Pin numbers for QFP160 in parenthesis.
SYMBOL
PIN
(1)
I/O
DESCRIPTION
BIT
XPD7 to
XPD0
C11, A11, B10, A10,
B9, A9, B8 and A8
(127, 128, 130, 131,
134, 135, 138 and 139)
A7 (143)
I/O X-port data: in output mode controlled by decoder section,
data format see Table 28; in input mode Y-C
B
-C
R
4 : 2 : 2
serial input data or luminance part of a 16-bit
Y-C
B
-C
R
4 : 2 : 2 input
I/O clock at expansion port: if output, then copy of LLC;
as input normally a double pixel clock of up to 32 MHz or a
gated clock (clock gated with a qualifier)
I/O data valid flag of the expansion port input (qualifier):
if output, then decoder (HREF and VGATE) gate (see
Fig.30)
O
data request flag = ready to receive, to work with optional
buffer in external device, to prevent internal buffer
overflow;
second function: input related task flag A/B
I/O horizontal reference signal for the X-port:
as output: HREF or HS from the decoder (see Fig.30);
as input: a reference edge for horizontal input timing and a
polarity for input field ID detection can be defined
I/O vertical reference signal for the X-port:
as output: V123 or field ID from the decoder,
see Figs 28 and 29;
as input: a reference edge for vertical input timing and for
input field ID detection can be defined
I
port control: switches X-port input 3-state
OFTS[2:0]
13H[2:0],
91H[7:0]
and C1H[7:0]
XCKS[92H[0]]
XCLK
XDQ
B7 (144)
XRDY
A6 (146)
XRQT[83H[2]]
XRH
C7 (141)
XRHS[13H[6]],
XFDH[92H[6]]
and
XDH[92H[2]]
XRVS[1:0]
13H[5:4],
XFDV[92H[7]]
and XDV[1:0]
92H[5:4]
XPE[1:0]
83H[1:0]
XRV
D8 (140)
XTRI
B11 (126)