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參數資料
| 型號： | SAA7109A |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | Codec |
| 英文描述： | HD-CODEC |
| 中文描述： | 高清解碼器 |
| 文件頁數： | 57/197頁 |
| 文件大?。?/td> | 983K |
| 代理商： | SAA7109A |
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2004 Jun 29
57
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
In VBI pass through operation the processing of prescaler
and vertical scaling has to be disabled, however the
horizontal fine scaling VPD can be activated. Upscaling
(oversampling, zooming), free of frequency folding, up to
factor 3.5 can be achieved, as required by some software
data slicing algorithms.
These raw samples are transported through the image
port as valid data and can be output as Y only format. The
lines are framed by SAV and EAV codes.
9.3.1
A
CQUISITION CONTROL AND TASK HANDLING
(
SUBADDRESSES
80H, 90H, 91H, 94H
TO
9FH
AND
C4H
TO
CFH)
The acquisition control receives horizontal and vertical
synchronization signals from the decoder section or from
the X port. The acquisition window is generated via pixel
and line counters at the appropriate places in the data
path. Only qualified pixels and lines (lines with qualified
pixel) are counted from the X port.
The acquisition window parameters are as follows:
Signal source selection: input video stream and formats
from the decoder, or from the X port (programming bits
SCSRC[1:0] 91H[5:4] and FSC[2:0] 91H[2:0])
Remark
: The input of raw VBI data from the internal
decoder should be controlled via the decoder output
formatter and the LCR registers (see Section 9.2)
Vertical offset: defined in lines of the video source,
parameter YO[11:0] 99H[3:0] 98H[7:0]
Vertical length: defined in lines of the video source,
parameter YS[11:0] 9BH[3:0] 9AH[7:0]
Vertical length: defined in number of target lines, as a
result of vertical scaling, parameter YD[11:0] 9FH[3:0]
9EH[7:0]
Horizontal offset: defined in number of pixels of the
video source, parameter XO[11:0] 95H[3:0] 94H[7:0]
Horizontal length: defined in number of pixels of the
video source, parameter XS[11:0] 97H[3:0] 96H[7:0]
Horizontal destination size: defined in target pixels after
fine scaling, parameter XD[11:0] 9DH[3:0] 9CH[7:0].
The source start offset XO(11:0) and YO(11:0) opens the
acquisition window, and the target size (XD11 to XD0,
YD11 to YD0) closes the window, however the window is
cut vertically if there are less output lines than required.
The trigger events for the pixel and line counts are the
horizontal and vertical reference edges as defined in
subaddress 92H.
The task handling is controlled by subaddress 90H;
see Section 9.3.1.2.
9.3.1.1
Input field processing
The trigger event for the field sequence detection from
external signals (X port) are defined in subaddress 92H.
The state of the scalers horizontal reference signal at the
time of the vertical reference edge is taken from the X port
asfieldsequenceidentifier(FID).Forexample,ifthefalling
edge of the XRV input signal is the reference and the state
of XRH input is logic 0 at that time, the detected field ID is
logic 0.
The bits XFDV[92H[7]] and XFDH[92H[6]] define the
detection event and state of the flag from the X port. For
the default setting of XFDV and XFDH at ‘00’ is taken from
the state of the horizontal input at the falling edge of the
vertical input.
The scaler gets corresponding field ID information directly
from the SAA7108AE; SAA7109AE decoder path.
The FID flag is used to determine whether the first or
second field of a frame is going to be processed within the
scaler, and it is also used as trigger conditions for the task
handling (see bits STRC[1:0] 90H[1:0]).
According to ITU 656, FID at logic 0 means first field of a
frame. To ease the application, the polarities of the
detection results on the X port signals and the internal
decoder ID can be changed via XFDH.
As the V sync from the decoder path has a half line timing
(due to the interlaced video signal), but the scaler
processing only recognises full lines, during 1st fields from
the decoder the line count of the scaler can possibly shift
by one line, compared to the 2nd field. This can be
compensated for by switching the vertical trigger event, as
defined by XDV0, to the opposite V sync edge or by using
the vertical scalers phase offsets. The vertical timing of the
decoder can be seen in Figs 30 and 31.
As the horizontal and vertical reference events inside the
ITU 656 data stream (from X port) and the real-time
reference signals from the decoder path are processed
differently, the trigger events for the input acquisition also
have to be programmed differently.
相關PDF資料 |
PDF描述 |
|---|---|
| SAA7109AE | HD-CODEC |
| SAA7110A | Digital Multistandard Colour Decoder(數字多標準彩色譯碼器) |
| SAA7111A | Enhanced Video Input Processor EVIP |
| SAA7111AH | Enhanced Video Input Processor EVIP |
| SAA7111AHZ | GT 13C 13#16 SKT PLUG |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SAA7109AE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
| SAA7109AE/V1,518 | 功能描述:視頻 IC HD- VIDEO CODEC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7109AE/V1,557 | 功能描述:視頻 IC HD- VIDEO CODEC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7109AE/V1/G | 功能描述:視頻 IC PC CODEC (W/OUT MICROVISION) RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7109AE/V1/G,518 | 功能描述:視頻 IC SAA7109AE/LBGA156/REEL13DP//V1 RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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