參數(shù)資料
型號(hào)： SAA7109A
廠商： NXP Semiconductors N.V.
元件分類(lèi)： Codec
英文描述： HD-CODEC
中文描述： 高清解碼器
文件頁(yè)數(shù)： 38/197頁(yè)
文件大?。?/td> 983K
代理商： SAA7109A
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2004 Jun 29
38
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
9.1.3.1
Chrominance path
The 9-bit CVBS or chrominance input signal is fed to the
input of a quadrature demodulator, where it is multiplied by
twotime-multiplexedsubcarriersignalsfromthesubcarrier
generation block 1 (0 and 90
°
phase relationship to the
demodulator axis). The frequency is dependent on the
chosen colour standard.
The time-multiplexed output signals of the multipliers are
low-pass filtered (low-pass 1). Eight characteristics are
programmable via LCBW3 to LCBW0 to achieve the
desired bandwidth for the colour difference signals (PAL,
NTSC) or the 0
°
and 90
°
FM signals (SECAM).
Thechrominancelow-pass 1characteristicalsoinfluences
the grade of cross-luminance reduction during horizontal
colour transients (large chrominance bandwidth means
strong suppression of cross-luminance). If the Y comb
filter is disabled when YCOMB = 0 the filter directly
influences the width of the chrominance notch within the
luminance path (large chrominance bandwidth means
wide chrominance notch resulting to lower luminance
bandwidth).
The low-pass filtered signals are fed to the adaptive comb
filter block. The chrominance components are separated
from the luminance via a two-line vertical stage (four lines
forPAL standards)andadecisionlogiccircuitbetweenthe
filtered and the non-filtered output signals: this block is
bypassed for SECAM signals. The comb filter logic can be
enabled independently for the succeeding luminance and
chrominance processing by YCOMB (subaddress 09H,
bit 6) and/or CCOMB (subaddress 0EH, bit 0). It is always
bypassed during VBI or raw data lines, programmable by
the LCRn registers (subaddresses 41H to 57H);
see Section 9.2.
The separated C
B
-C
R
components are further processed
by a second filter stage (low-pass 2) to modify the
chrominance bandwidth without influencing the luminance
path. It’s characteristic is controlled by CHBW
(subaddress 10H, bit 3). For the complete transfer
characteristic of low-pass filters 1 and 2 see
Figs 19 and 20.
The SECAM processing (bypassed for QAM standards)
contains the following blocks:
Baseband ‘bell’ filters to reconstruct the amplitude and
phase equalized 0
°
and 90
°
FM signals
Phase demodulator and differentiator
(FM demodulation)
De-emphasis filter to compensate the pre-emphasized
input signal, including frequency offset compensation
(DB or DR white carrier values are subtracted from the
signal, controlled by the SECAM switch signal).
The succeeding chrominance gain control block amplifies
or attenuates the C
B
-C
R
signal according to the required
ITU 601/656 levels. It is controlled by the output signal
from the amplitude detection circuit within the burst
processing block.
The burst processing block provides the feedback loop of
the chrominance PLL and contains the following:
Burst gate accumulator
Colour identification and killer
Comparisonnominal/actualburstamplitude(PAL/NTSC
standards only)
Loop filter chrominance gain control (PAL/NTSC
standards only)
Loop filter chrominance PLL (only active for PAL/NTSC
standards)
PAL/SECAM sequence detection, H/2-switch
generation.
The increment generation circuit produces the Discrete
Time Oscillator (DTO) increment for both subcarrier
generation blocks. It contains a division by the increment
of the line-locked clock generator to create a stable
phase-locked sine signal under all conditions (e.g. for
non-standard signals).
The PAL delay line block eliminates crosstalk between the
chrominance channels in accordance with the PAL
standard requirements. For NTSC colour standards, the
delay line can be used as an additional vertical filter.
If desired, it can be switched off by DCVF = 1. It is always
disabledduring VBIor rawdatalinesprogrammable bythe
LCRn registers (subaddresses 41H to 57H); see
Section 9.2. The embedded line delay is also used for
SECAM recombination (cross-over switches).
相關(guān)PDF資料
PDF描述
SAA7109AE HD-CODEC
SAA7110A Digital Multistandard Colour Decoder(數(shù)字多標(biāo)準(zhǔn)彩色譯碼器)
SAA7111A Enhanced Video Input Processor EVIP
SAA7111AH Enhanced Video Input Processor EVIP
SAA7111AHZ GT 13C 13#16 SKT PLUG
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA7109AE 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:HD-CODEC
SAA7109AE/V1,518 功能描述:視頻 IC HD- VIDEO CODEC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
SAA7109AE/V1,557 功能描述:視頻 IC HD- VIDEO CODEC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
SAA7109AE/V1/G 功能描述:視頻 IC PC CODEC (W/OUT MICROVISION) RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
SAA7109AE/V1/G,518 功能描述:視頻 IC SAA7109AE/LBGA156/REEL13DP//V1 RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
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