參數(shù)資料
型號(hào): SAA7105H
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Digital video encoder
文件頁(yè)數(shù): 41/71頁(yè)
文件大小: 354K
代理商: SAA7105H
2004 Mar 04
41
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 68
Subaddress 84H
Table 69
Logic levels and function of PCLE
Table 70
Logic levels and function of PCLI
Table 71
Subaddress 85H
Table 72
Subaddresses 90H and 94H
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
DCLK
0
pixel clock input is differential, pin PIXCLKI receives the inverted clock; default after
reset
pixel clock input is single ended, pin PIXCLKI has no function
pixel clock generator runs free; default after reset
pixel clock generator gets synchronized with the vertical sync
input FIFO gets reset explicitly at falling edge
input FIFO gets reset every field; default after reset
input FIFO is active
input FIFO is bypassed; default after reset
controls the divider for the external pixel clock; see Table 69
controls the divider for the internal pixel clock; see Table 70
1
0
1
0
1
0
1
PCLSY
IFRA
IFBP
PCLE
PCLI
DATA BYTE
DESCRIPTION
PCLE1
PCLE0
0
0
1
1
0
1
0
1
divider ratio for PIXCLK output is 1
divider ratio for PIXCLK output is 2; default after reset
divider ratio for PIXCLK output is 4
divider ratio for PIXCLK output is 8
DATA BYTE
DESCRIPTION
PCLI1
PCLI0
0
0
1
1
0
1
0
1
divider ratio for internal PIXCLK is 1
divider ratio for internal PIXCLK is 2; default after reset
divider ratio for internal PIXCLK is 4
not allowed
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
EIDIV
0
1
set to logic 0 if DVO compliant signals are applied; default after reset
set to logic 1 if non-DVO compliant signals are applied
threshold for FIFO internal transfers; nominal value is 8; default after reset
FILI
DATA BYTE
DESCRIPTION
XOFS
horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite
blanking (CBO) output
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