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參數(shù)資料
| 型號(hào)： | SAA7105H |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Digital video encoder |
| 文件頁數(shù)： | 37/71頁 |
| 文件大?。?/td> | 354K |
| 代理商： | SAA7105H |
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2004 Mar 04
37
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 48
Subaddresses 63H to 66H (four bytes to program subcarrier frequency)
Note
1.
Examples:
a) NTSC M: f
fsc
= 227.5, f
llc
= 1716
→
FSC = 569408543 (21F07C1FH).
b) PAL B/G: f
fsc
= 283.7516, f
llc
= 1728
→
FSC = 705268427 (2A098ACBH).
Table 49
Subaddresses 67H to 6AH
Table 50
Subaddresses 6CH and 6DH
Table 51
Subaddress 6DH
Table 52
Subaddress 6EH
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
FSC0 to FSC3 f
fsc
= subcarrier frequency (in multiples
of line frequency); f
llc
= clock frequency
(in multiples of line frequency)
;
note 1
FSC3 = most significant byte;
FSC0 = least significant byte
DATA BYTE
DESCRIPTION
REMARKS
L21O0
L21O1
L21E0
L21E1
first byte of captioning data, odd field
second byte of captioning data, odd field
first byte of extended data, even field
second byte of extended data, even field
LSBs of the respective bytes are encoded immediately
after run-in and framing code, the MSBs of the respective
bytes have to carry the parity bit, in accordance with the
definition of line 21 encoding format.
DATA BYTE
DESCRIPTION
HTRIG
sets the horizontal trigger phase related to chip-internal horizontal input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases
delays of all internally generated timing signals; the default value is 0
DATA BYTE
DESCRIPTION
VTRIG
sets the vertical trigger phase related to chip-internal vertical input
increasingVTRIGdecreasesdelaysofallinternallygeneratedtimingsignals,measuredinhalflines;
variation range of VTRIG = 0 to 31 (1FH); the default value is 0
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
NVTRIG
0
1
0
1
values of the VTRIG register are positive
values of the VTRIG register are negative
encoder in normal operation mode; default after reset
output signal is forced to blanking level
selects the phase reset mode of the colour subcarrier generator; see Table 53
selects the delay on luminance path with reference to chrominance path; see Table 54
field length control; see Table 55
BLCKON
PHRES
LDEL
FLC
FSC
round
f
llc
f
2
32
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7105H | Digital video encoder |
| SAA7108 | PC-CODEC |
| SAA7109 | PC-CODEC |
| SAA7108E | PC-CODEC |
| SAA7109E | PC-CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7105H/V1,518 | 功能描述:視頻 IC PC DENC WO MACROVISION LICENSE RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7105H/V1,557 | 功能描述:視頻 IC PC GRAPHICS 85MHZ RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7105HBG | 功能描述:視頻 IC PC GRAPHICS 85MHZ ENCODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7108 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PC-CODEC |
| SAA7108AE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
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