
2004 Mar 04
39
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 58
Subaddresses 70H to 72H
Table 59
Subaddress 73H
Table 60
Subaddress 74H
Table 61
Subaddress 75H
Table 62
Subaddresses 76H, 77H and 7CH
DATA BYTE
DESCRIPTION
ADWHS
active display window horizontal start; defines the start of the active TV display portion after the border
colour
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
active display window horizontal end; defines the end of the active TV display portion before the
border colour
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
ADWHE
DATA BYTE
DESCRIPTION
REMARKS
TTXHS
start of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0);
see Fig.15
TTXHS = 42H; is default after
reset if strapped to PAL
TTXHS = 54H; is default after
reset if strapped to NTSC
DATA BYTE
DESCRIPTION
REMARKS
TTXHD
indicates the delay in clock cycles between rising edge of TTXRQ
output signal on pin TTXRQ_XCLKO2 (CLK2EN = 0) and valid data at
pin TTX_SRES
minimum value: TTXHD = 2;
is default after reset
DATA BYTE
DESCRIPTION
CSYNCA
advanced composite sync against RGB output from 0 XTAL clocks to 31 XTAL clocks
DATA BYTE
DESCRIPTION
REMARKS
TTXOVS
first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2
(CLK2EN = 0) in odd field
line = (TTXOVS + 4) for M-systems
line = (TTXOVS + 1) for other systems
TTXOVS = 05H; is default
after reset if strapped to PAL
TTXOVS = 06H; is default
after reset if strapped to
NTSC
TTXOVE = 16H; is default
after reset if strapped to PAL
TTXOVE = 10H; is default
after reset if strapped to
NTSC
TTXOVE
last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2
(CLK2EN = 0) in odd field
line = (TTXOVE + 3) for M-systems
line = TTXOVE for other systems