- 您現(xiàn)在的位置：買賣IC網 > PDF目錄372112 > SAA7105H (NXP Semiconductors N.V.) Digital video encoder PDF資料下載
參數(shù)資料
| 型號： | SAA7105H |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Digital video encoder |
| 文件頁數(shù)： | 10/71頁 |
| 文件大?。?/td> | 354K |
| 代理商： | SAA7105H |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁
2004 Mar 04
10
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
7.1
Reset conditions
To activate the reset a pulse at least of 2 crystal clocks
duration is required.
During reset (RESET = LOW) plus an extra 32 crystal
clock periods, FSVGC, VSVGC, CBO, HSVGC and
TTX_SRES are set to input mode and HSM_CSYNC and
VSM are set to 3-state. A reset also forces the I
2
C-bus
interface to abort any running bus transfer and sets it into
receive condition.
After reset, the state of the I/Os and other functions is
defined by the strapping pins until an I
2
C-bus access
redefines the corresponding registers; see Table 1.
Table 1
Strapping pins
7.2
Input formatter
The input formatter converts all accepted PD input data
formats, either RGB or Y-C
B
-C
R
, to a common internal
RGB or Y-C
B
-C
R
data stream.
When double-edge clocking is used, the data is internally
split into portions PPD1 and PPD2. The clock edge
assignment must be set according to the I
2
C-bus control
bits SLOT and EDGE for correct operation.
If Y-C
B
-C
R
is being applied as a 27 Mbyte/s data stream,
the output of the input formatter can be used directly to
feed the video encoder block.
The horizontal upscaling is supported via the input
formatter. According to the programming of the pixel clock
dividers (see Section 7.10), it will sample up the data
stream to 1
×
, 2
×
or 4
×
the input data rate. An optional
interpolation filter is available. The clock domain transition
is handled by a 4 entries wide FIFO which gets initialized
every field or explicitly at request. A bypass for the FIFO is
available, especially for high input data rates.
7.3
RGB LUT
The three 256 byte RAMs of this block can be addressed
by three 8-bit wide signals, thus it can be used to build any
transformation, e.g. a gamma correction for RGB signals.
In the event that the indexed colour data is applied, the
RAMs are addressed in parallel.
The LUTs can either be loaded by an I
2
C-bus write access
or can be part of the pixel data input through the PD port.
In the latter case, 256
×
3 bytes for the R, G and B LUT are
expected at the beginning of the input video line, two lines
before the line that has been defined as first active line,
until the middle of the line immediately preceding the first
active line. The first 3 bytes represent the first RGB LUT
data, and so on.
7.4
Cursor insertion
A 32
×
32 dots cursor can be overlaid as an option; the bit
map of the cursor can be uploaded by an I
2
C-bus write
access to specific registers or in the pixel data input
through the PD port. In the latter case, the 256 bytes
defining the cursor bit map (2 bits per pixel) are expected
immediately following the last RGB LUT data in the line
preceding the first active line.
The cursor bit map is set up as follows: each pixel
occupies 2 bits. The meaning of these bits depends on the
CMODE I
2
C-bus register as described in Table 4.
Transparent means that the input pixels are passed
through, the ‘cursor colours’ can be programmed in
separate registers.
The bit map is stored with 4 pixels per byte, aligned to the
least significant bit. So the first pixel is in bits 0 and 1, the
next pixel in bits 3 and 4 and so on. The first index is the
column, followed by the row; index 0,0 is the upper left
corner.
PIN
TIED
PRESET
FSVGC
LOW
NTSC M encoding, PIXCLK
fits to 640
×
480 graphics
input
HIGH PAL B/G encoding, PIXCLK
fits to 640
×
480 graphics
input
LOW
4 : 2 : 2 Y-C
B
-C
R
graphics
input (format 0)
HIGH 4 : 4 : 4 RGB graphics input
(format 3)
LOW
input demultiplex phase:
LSB = LOW
HIGH input demultiplex phase:
LSB = HIGH
LOW
input demultiplex phase:
MSB = LOW
HIGH input demultiplex phase:
MSB = HIGH
slave (FSVGC, VSVGC and
HSVGC are inputs, internal
colour bar is active)
HIGH master (FSVGC, VSVGC
and HSVGC are outputs)
VSVGC
CBO
HSVGC
TTXRQ_XCLKO2 LOW
相關PDF資料 |
PDF描述 |
|---|---|
| SAA7105H | Digital video encoder |
| SAA7108 | PC-CODEC |
| SAA7109 | PC-CODEC |
| SAA7108E | PC-CODEC |
| SAA7109E | PC-CODEC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7105H/V1,518 | 功能描述:視頻 IC PC DENC WO MACROVISION LICENSE RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7105H/V1,557 | 功能描述:視頻 IC PC GRAPHICS 85MHZ RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7105HBG | 功能描述:視頻 IC PC GRAPHICS 85MHZ ENCODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7108 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PC-CODEC |
| SAA7108AE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
發(fā)布緊急采購，3分鐘左右您將得到回復。