參數(shù)資料
型號(hào): SAA7105E
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: Digital video encoder
中文描述: COLOR SIGNAL ENCODER, PBGA156
封裝: 15 X 15 MM, 1.15 MM HEIGHT, PLASTIC, MS-034, SOT-472-1, BGA-156
文件頁數(shù): 7/70頁
文件大小: 360K
代理商: SAA7105E
2004 Mar 04
7
Philips Semiconductors
Product specification
Digital video encoder
SAA7104E; SAA7105E
Notes
1.
2.
Pin type: I = input, O = output, S = supply, pu = pull-up.
In accordance with the “IEEE1149.1”standard the pins TDI, TMS, TCK and TRST are input pins with an internal
pull-up resistor and TDO is a 3-state output pin.
For board design without boundary scan implementation connect TRST to ground.
This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test
Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
The pins FSVGC, VSVGC, CBO, HSVGC and TTXRQ_XCLKO2 are used for bootstrapping; see Section 7.1.
3.
4.
5.
VSM
D7
O
vertical synchronization output to monitor (non-interlaced auxiliary
RGB)
horizontal synchronization output to monitor (non-interlaced
auxiliary RGB) or composite sync for RGB-SCART
test clock input for BST; note 2
I
2
C-bus serial clock input
horizontal synchronization output to VGC (optional input); note 5
to be reserved for future applications
vertical synchronization output to VGC (optional input); note 5
pixel clock input (looped through)
MSB
4 with C
B
-Y-C
R
4 : 2 : 2; see Tables 9 to 14 for
pin assignment
digital supply voltage 1 for pins PD11 to PD0, PIXCLKI, PIXCLKO,
FSVGC, VSVGC, HSVGC, CBO and TVD
interrupt if TV is detected at DAC output
frame synchronization output to Video Graphics Controller (VGC)
(optional input); note 5
I
2
C-bus serial data input/output
composite blanking output to VGC; active LOW; note 5
pixel clock output to VGC
MSB
5 with C
B
-Y-C
R
4 : 2 : 2; see Tables 9 to 14 for
pin assignment
MSB
6 with C
B
-Y-C
R
4 : 2 : 2; see Tables 9 to 14 for
pin assignment
MSB
7 with C
B
-Y-C
R
4 : 2 : 2; see Tables 9 to 14 for
pin assignment
HSM_CSYNC
D8
O
TCK
SCL
HSVGC
reserved
VSVGC
PIXCLKI
PD3
E1
E2
E3
E12
F1
F2
F3
I/pu
I
I/O
I/O
I
I
V
DDD1
F4
S
TVD
FSVGC
F12
G1
O
I/O
SDA
CBO
PIXCLKO
PD2
G2
G3
G4
H1
I/O
I/O
O
I
PD1
H2
I
PD0
H3
I
SYMBOL
PIN
TYPE
(1)
DESCRIPTION
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