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參數(shù)資料
| 型號： | SAA7105E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Digital video encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PBGA156 |
| 封裝： | 15 X 15 MM, 1.15 MM HEIGHT, PLASTIC, MS-034, SOT-472-1, BGA-156 |
| 文件頁數(shù)： | 19/70頁 |
| 文件大?。?/td> | 360K |
| 代理商： | SAA7105E |
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2004 Mar 04
19
Philips Semiconductors
Product specification
Digital video encoder
SAA7104E; SAA7105E
The following Sections give the set of equations required
to program the IC for the most common application: A post
processor in master mode with non-interlaced video input
data.
Some variables are defined below:
InPix: the number of active pixels per input line
InPpl: the length of the entire input line in pixel clocks
InLin: the number of active lines per input field/frame
TPclk: the pixel clock period
RiePclk: the ratio of internal to external pixel clock
OutPix: the number of active pixels per output line
OutLin: the number of active lines per output field
TXclk: the encoder clock period (37.037 ns).
7.20.1
TV
DISPLAY WINDOW
At 60 Hz, the first visible pixel has the index 256,
710 pixels can be encoded; at 50 Hz, the index is 284,
702 pixels can be visible.
The output lines should be centred on the screen. It should
be noted that the encoder has 2 clocks per pixel;
see Table 59.
ADWHS = 256 + 710
OutPix (60 Hz);
ADWHS = 284 + 702
OutPix (50 Hz);
ADWHE = ADWHS + OutPix
×
2 (all frequencies)
For vertical, the procedure is the same. At 60 Hz, the first
line with video information is number 19, 240 lines can be
active. For 50 Hz, the numbers are 23 and 287;
see Table 65.
(60 Hz);
(50 Hz);
LAL = FAL + OutLin (all frequencies)
Most TV sets use overscan, and not all pixels respectively
lines are visible. There is no standard for the factor, it is
highly recommended to make the number of output pixels
and lines adjustable. A reasonable underscan factor is
10%, giving approximately 640 output pixels per line.
7.20.2
I
NPUT FRAME AND PIXEL CLOCK
The total number of pixel clocks per line and the input
horizontal offset need to be chosen next. The only
constraint is that the horizontal blanking has at least
10 clock pulses.
The required pixel clock frequency can be determined in
the following way: Due to the limited internal FIFO size, the
input path has to provide all pixels in the same time frame
as the encoders vertical active time. The scaler also has to
process the first and last border lines for the anti-flicker
function. Thus:
1716
×
integer----------------------
OutLin
(60 Hz)
(50 Hz)
and for the pixel clock generator
TPclk
(all frequencies);
see Tables 68,70 and 71.ThedividerPCLEshouldbeset
according to Table 70. PCLI may be set to a lower or the
same value. Setting a lower value means that the internal
pixel clock is higher and the data get sampled up. The
difference may be 1 at 640
×
480 pixels resolution and 2 at
resolutions with 320 pixels per line as a rule of thumb. This
allows horizontal upscaling by a maximum factor of 2
respectively 4 (this is the parameter RiePclk).
(all frequencies)
The equations ensure that the last line of the field has the
full number of clock cycles. Many graphic controllers
require this. Note that the bit PCLSY needs to be set to
ensure that there is not even a fraction of a clock left at the
end of the field.
7.20.3
H
ORIZONTAL SCALER
XOFS can be chosen arbitrarily, the condition being that
XOFS + XPIX
≤
HLEN is fulfilled. Values given by the
VESA display timings are preferred.
HLEN = InPpl
×
RiePclk
1
InPix
InPix
XINC needs to be rounded up, it needs to be set to 0 for a
scaling factor of 1.
FAL
19
240
OutLin
2
2
–
+
=
FAL
23
287
–
+
=
TPclk
TXclk
2
+
×
InPpl
262.5
×
×
----------------262.5
=
TPclk
×
TXclk
2
×
InPpl
-OutLin
312.5
×
----------------3intege1728
=
PCL
TXclk
2
20
PCLE
+
×
=
PCLI
PCLE
2
log
log
–
=
XPIX
-----2
RiePclk
×
=
XINC
OutPix
RiePclk
---4096
×
=
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7104H | GT 38C 38#12 PIN PLUG |
| SAA7105H | Digital video encoder |
| SAA7105H | Digital video encoder |
| SAA7108 | PC-CODEC |
| SAA7109 | PC-CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7105E/V1/G | 功能描述:視頻 IC PC-DENC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7105E/V1/G,518 | 功能描述:視頻 IC PC-DENC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7105E/V1/G,557 | 功能描述:視頻 IC PC-DENC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7105E/V1/G-T | 功能描述:視頻 IC PC-DENC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7105E/V1/S1,518 | 功能描述:視頻 IC DIGITAL VIDEO ENCODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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