2002 May 06
47
Philips Semiconductors
Objective specification
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA567x; SAA569x
17 I
2
C-BUS SERIAL I/O
The I
2
C-bus consists of a serial data line (SDA) and a
serial clock line (SCL). The definition of the I
2
C-bus
protocol can be found in “The I
2
C-bus and how to use it
(including specification)”. Philips document ordering
number 9398 393 40011.
The device operates in four modes:
Master transmitter
Master receiver
Slave transmitter
Slave receiver.
The microcontroller peripheral is controlled by the Serial
Control SFR (S1CON) and its status is indicated by the
Status SFR (S1STA). Information is transmitted/received
to/from the I
2
C-bus using the Data SFR (S1DAT). The
Slave Address SFR (S1ADR) is used to configure the
slave address of the peripheral.
The byte level I
2
C-bus serial port is identical to the I
2
C-bus
serial port on the P8xC558, except for the clock rate
selection bits CR<2:0>. The operation of the subsystem is
described in detail in the “P8xC558 data sheet”.
17.1
I
2
C-bus modes
Three different I
2
C-bus selection tables for CR<2:0> can
be configured using the ROMBK SFR (IIC_LUT<1:0>), as
shown in Table 17.
17.1.1
N
OMINAL MODE
(IIC_LUT<1:0> = 00)
This option accommodates the P8xC558 I
2
C-bus, refer to
“Handbook IC20, 80C51-Based 8-Bit Microcontrollers”
The various serial rates are shown in Table 17:
Table 17
I
2
C-bus serial rates in ‘P8xC558 nominal mode’
17.1.2
F
AST MODE
(IIC_LUT<1:0> = 01)
This option accommodates the P8xC558 I
2
C-bus doubled
rates, as shown in Table 18.
Table 18
I
2
C-bus serial rates in ‘P8xC558 fast mode’
17.1.3
S
LOW MODE
’ (IIC_LUT<1:0> = 10)
This option accommodates the P8xC558 I
2
C-bus rates,
divided by 2, see Table 19.
Table 19
I
2
C-bus serial rates ‘P8xC558 slow mode’
17.2
I
2
C-bus port selection
Two I
2
C-bus ports are available: SCL0/SDA0 and
SCL1/SDA1. The ports are selected by using TXT21.I
2
C
Port 0 and TXT21.I
2
C Port 1. When a port is enabled, any
information transmitted from the device goes onto the
enabled port. Information transmitted to the device can
only be acted on if the port is enabled.
If both ports are enabled, then data transmitted from the
device is seen on both ports. However, data transmitted to
the device on one port cannot be seen on the other port.
CR2
CR1
CR0
12 MHz
DIVISOR
I
2
C-BUS BIT
FREQUENCY (kHz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
60
200
7.5
300
400
50
3.75
75
100
1600
40
30
240
3200
160
120
CR2
CR1
CR0
12 MHz
DIVISOR
I
2
C-BUS BIT
FREQUENCY (kHz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
30
800
20
15
120
1600
80
60
400
15
600
800
100
7.5
150
200
CR2
CR1
CR0
12 MHz
DIVISOR
I
2
C-BUS BIT
FREQUENCY (kHz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
120
3200
80
60
480
6400
320
240
100
3.75
150
200
25
1.875
37.5
50