參數(shù)資料
型號: SAA567X
廠商: NXP Semiconductors N.V.
英文描述: Enhanced TV microcontrollers with On-Screen Display (OSD)
中文描述: 與微控制器在強(qiáng)化電視屏幕顯示(OSD)
文件頁數(shù): 23/116頁
文件大小: 532K
代理商: SAA567X
2002 May 06
23
Philips Semiconductors
Objective specification
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA567x; SAA569x
REN
Enables serial reception. Set by software to enable reception. Cleared by
software to disable reception.
Is the 9
th
data bit that will be transmitted in Modes 2 and 3. Set or cleared by
software as desired.
In Modes 2 and 3, RB8 is the 9
th
data bit that was received. In Mode 1, if SM2 is
logic 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used.
Loading of RB8 in Modes 1, 2 and 3 depends on SM2.
Is the transmit interrupt flag. Set by hardware at the end of the 8
th
bit time in
Mode 0, or at the beginning of the stop bit in the other modes. Must be cleared
by software.
Is the receive interrupt flag. Set by hardware at the end of the 8
th
bit time in
Mode 0, or halfway through the stop bit time in the other modes, in any serial
reception (except see SM2). Must be cleared by software.
TB8
RB8
TI
RI
I
2
C-bus Slave Address Register (S1ADR)
ADR6 to ADR0
GC
I
2
C-bus slave address to which the device will respond
enable I
2
C-bus general call address (logic 1)
I
2
C-bus Control Register (S1CON)
CR2 to CR0
clock rate bits; CR<2:0>: (for nominal mode)
000 = 200 kHz bit rate
001 = 7.5 kHz bit rate
010 = 300 kHz bit rate
011 = 400 kHz bit rate
100 = 50 kHz bit rate
101 = 3.75 kHz bit rate
110 = 75 kHz bit rate
111 = 100 kHz bit rate
enable I
2
C-bus interface (logic 1)
START flag:
When this bit is set in slave mode, the hardware checks the I
2
C-bus
and generates a START condition if the bus is free or after the bus becomes free.
If the device operates in master mode, it will generate a repeated START
condition.
STOP flag:
If this bit is set in a master mode, a STOP condition is generated. A
STOP condition detected on the I
2
C-bus clears this bit. This bit may also be set
in slave mode, to recover from an error condition. In this case, no STOP
condition is generated to the I
2
C-bus, but the hardware releases the SDA and
SCL lines and switches to the not selected receiver mode. The STOP flag is
cleared by the hardware.
ENSI
STA
STO
BITS
FUNCTION
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