參數(shù)資料
型號(hào)： SAA3500H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Digital audio broadcast channel decoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, MO-112, SOT-317-1, QFP-100
文件頁(yè)數(shù)： 5/32頁(yè)
文件大?。?/td> 156K
代理商： SAA3500H
2000 Jun 14
5
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
7
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
ADC
AIF
V
SSA
ADE
V
DDA
INP[0:9]
ADCLK
IQS
1
2
3
99
100
8 to 17
19
20
input
input
ground analog supply ground
input
analog-to-digital converter enable (active LOW)
supply
analog voltage supply (+3.3 V)
input
2048 kHz IF or baseband digital parallel input data (8 or 10 bits)
output
analog-to-digital clock output 8192 kHz if BYP = HIGH, 4096 kHz if BYP = LOW
input
clock signal indicating I or Q baseband data if BYP = LOW;
signal for swapping I and Q data bytes if BYP = HIGH
input
IF input stage bypass (active LOW)
input
frame sync input (LOW indicates DAB null symbol detection)
output
null detector/frame sync output (LOW indicates DAB null symbol position)
output
AGC synchronization lock indicator (HIGH if synchronized)
output
AGC level comparator output (HIGH if input sample > reference level, else LOW)
input
oscillator or system clock input, 24576 kHz
output
oscillator output
output
master clock output, 24576 kHz
supply
digital supply ground
analog-to-digital converter DC input
analog-to-digital converter IF input
BYP
FSI
FSO
SLI
AGC
OSCI
OSCO
MCLK
V
SS
21
22
23
24
25
4
5
41
7, 18,
26, 40,
60, 80
and 94
6, 28,
42 and
79
92
32 to 39 output
27
29
30
31
51
52
53
54
55
62 to 68 output
81 to 91 output
61
69
70
71 to 78 I/O
V
DD
supply
digital voltage supply (+3.3 V)
TEST
OUT[0:7]
OCLK
OIQ
OCIR
OEN
CFIC
CMODE
CDATA
CCLK
RESET
A[17:11]
A[10:0]
WR
RD
A17
D[0:7]
input
connect to ground for proper operation
baseband or channel impulse response output
output data clock (negative edge indicates new data)
output I or Q select signal if OCIR = HIGH, or frame trigger if OCIR = LOW
output select: baseband if OCIR = HIGH, CIR if OCIR = LOW
output enable (active LOW)
microcontroller interface signal indicating Fast Information Channel (FIC) processing
microcontroller interface mode input (only L3-bus)
microcontroller interface serial data I
2
C-bus or L3-bus (5 V tolerant)
microcontroller interface clock input I
2
C-bus or L3-bus
chip reset input (active LOW)
address outputs external RAM
address outputs external RAM
write data to RAM (active LOW)
read data from RAM (active LOW)
address bit 17 inverted for second RAM (128k
×
8)
data input/output external RAM
output
output
input
input
output
input
I/O
input
input
output
output
output
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