參數(shù)資料
型號: SAA3500H
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Digital audio broadcast channel decoder
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, MO-112, SOT-317-1, QFP-100
文件頁數(shù): 21/32頁
文件大?。?/td> 156K
代理商: SAA3500H
2000 Jun 14
21
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
Notes
1.
2.
In a real application, the clock frequency may vary in a range of
±
50 ppm due to timing synchronization.
T = 4
×
OSC cycle time, i.e., T = 163 ns at f
osc
= 24.576 MHz.
L3-
BUS MICROCONTROLLER TO SLAVE DEVICE
; see Figs 26 and 28
t
cL
t
cH
t
d1
L3CLK LOW time
L3CLK HIGH time
L3MODE set-up time before first L3CLK
LOW
L3DATA hold time after L3CLK HIGH
L3MODE hold time after last L3CLK HIGH
L3DATA set-up time before L3CLK HIGH
L3MODE LOW time
note 2
note 2
T + 10
T + 10
10
ns
ns
ns
t
h1
t
h2
t
su
t
L
L3-
BUS SLAVE DEVICE TO MICROCONTROLLER
; see Fig.27
10
15
T + 10
T + 10
ns
ns
ns
ns
note 2
note 2
t
d2
t
d3
t
d4
t
d5
t
h3
I
2
C-
BUS INPUTS
/
OUTPUT
(CDATA
AND
CCLK)
L3MODE HIGH to L3DATA enabled time
L3MODE HIGH to L3DATA stable time
L3CLK HIGH to L3DATA stable time
L3MODE LOW to L3DATA disabled time
L3DATA hold time after L3CLK HIGH
0
0
T
20
20
2T + 30
20
ns
ns
ns
ns
ns
note 2
note 2
t
f,I2C
f
CCLK
output fall time
CCLK clock frequency
250
400
ns
kHz
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ADCLK
INP[9:0]
IQS
t
CH,ADCLK
T
cy,ADCLK
t
CL,ADCLK
t
h,IQS
t
h,INP
Fig.15 Baseband input timing (BYP = LOW).
ADCLK
INP[9:0]
t
CH,ADCLK
T
cy,ADCLK
t
CL,ADCLK
t
d,INP
t
h,INP
Fig.16 IF input timing [BYP = HIGH, IQS = LOW (no swap) or HIGH (swap)].
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