參數(shù)資料
型號(hào)： SAA3500H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Digital audio broadcast channel decoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, MO-112, SOT-317-1, QFP-100
文件頁(yè)數(shù)： 12/32頁(yè)
文件大?。?/td> 156K
代理商： SAA3500H
2000 Jun 14
12
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
In case SFCO data output is not desired, a particular ‘RDI plus’ mode can be selected, which provides a continuous
6144 kHz clock on RDC, synchronous to the bi-phase RDI data and accompanied by a fixed word select signal, to allow
RDI source reception without an extra clock recovery circuit. Output data shall be latched on the rising edge of RDC.
9.7
Microcontroller interface
The microcontroller interface of the SAA3500H operates in one of two distinct modes of operation: I
2
C-bus or L3-bus.
Mode setting is determined at initialization, as described in Fig.12. On either control bus data are transferred in 8-bit
packets, or bytes.
The interface uses three signals and the function in the L3-bus mode or I
2
C-bus mode is indicated in Table 3.
Table 3
Control bus modes
During a hard reset of the device, the microcontroller interface mode is determined. As a consequence, the interface
cannot be used while the reset signal is asserted. Mandatory action must be taken for correct microcontroller interface
start-up at a hard reset, as explained in Fig.12.
SIGNAL
L3-BUS MODE
I
2
C-BUS MODE
DIRECTION
DESCRIPTION
CDATA
CCLK
CMODE
L3DATA
L3CLK
L3MODE
SDA
SCL
none
input/output
input
input
microcontroller interface serial data
microcontroller interface bit clock
microcontroller interface mode select
RDO
Fig.10 RDI output (normal mode, RDE = LOW).
RDC
SFCO
RDO
Channel 2 (32 bits)
Channel 1 (32 bits)
Fig.11 RDI output (RDI plus mode, RDE = LOW).
RESET
CCLK
CMODE
L3-bus mode
I
2
C-bus mode
phase 1
phase 2
phase 3
Fig.12 Microcontroller interface initialization procedure.
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