May 1994
5
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
A4
V
SS3
V
DD3
A5
A6
A7
A12/PINO5
A14/PINO1
A16/PINO3
A15/PINO4
WEN
A13/PINO2
A8
V
DD4
V
SS4
A9/CAS
A11
SPEED
PINO2
WDATA
TCLOCK
V
SS5
V
DD5
TEST2
RDMUX
V
ref(p)
V
ref(n)
SUBSTR
BIAS
V
SSA
V
DDA
ANAEYE
RDSYNC
V
DD6
V
SS6
CHTST1
CHTST2
TEST0
TEST1
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
address SRAM; address DRAM
digital ground
digital supply voltage
address SRAM; address DRAM
address SRAM; address DRAM
address SRAM; address DRAM
address SRAM; Port expander output 5
address SRAM; Port expander output 1
address SRAM; Port expander output 3
address SRAM; Port expander output 4
write enable for RAM
address SRAM; Port expander output 2
address SRAM; address DRAM
digital supply voltage
digital ground
address SRAM; CAS for DRAM
address SRAM
Pulse Width Modulation (PWM) capstan control output for deck O
t
(1 mA)
Port expander output 2
serial output to write amplifier
3.072 MHz clock output for tape I/O
digital ground
digital supply voltage
TEST mode select; do not connect
analog multiplexed input from read amplifier
ADC positive reference voltage
ADC negative reference voltage
substrate connection
bias current for ADC
analog ground
analog supply voltage
analog eye pattern output
synchronization output for read amplifier
digital supply voltage
digital ground
channel test pin 1
channel test pin 2
TEST mode select; do not connect
TEST mode select; do not connect
O (2 mA)
S
S
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
S
S
O (2 mA)
O (2 mA)
O
t
(1 mA)
O (1 mA)
O (1 mA)
S
S
I
pd
I
A
I
A
I
A
I
A
I
A
S
S
O
A
O (1 mA)
S
S
O (1 mA)
O (1 mA)
I
pd
I
pd
SYMBOL
PIN
DESCRIPTION
TYPE
(1)
QFP80
TQFP80