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參數(shù)資料
| 型號： | SAA3323GP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Drive processor for DCC systems |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80 |
| 文件頁數(shù)： | 24/56頁 |
| 文件大?。?/td> | 274K |
| 代理商： | SAA3323GP |
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May 1994
24
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Read/write connections
TCLOCK
This output pin is the 3.072 MHz clock output for the read
and write amplifiers, it should be connected directly to the
WCLOCK pin of the write amplifier and to the RDCLK pin
of the read amplifier.
RDMUX
This input pin carries the time multiplexed analog tape
channel signals from the read amplifier.
V
ref(n)
AND
V
ref(p)
These are the lower and upper voltage reference inputs for
the ADC in the digital equalizer part of SAA3323.
BIAS
This pin defines a bias current for the ADC. It should be
connected to the analog supply voltage V
DDA
via a 47 k
resistor.
RDSYNC
This output line provides synchronization information for
the read Amplifier data transfers. The relationship between
TCLOCK, RDSYNC and the channel information carried
by the RDMUX line is given in Fig.20. This pin should be
connected directly to the RDSYNC pin of the read
amplifier. When the digital equalizer in SAA3323 is in
search mode this pin will be HIGH ensuring that only the
AUX channel is processed by the SAA3323.
WDATA
This output pin is the multiplexed data and control line for
the write amplifier. Figure 21 shows the manner in which
this information is multiplexed onto WDATA. The WDATA
pin should be connected directly to the WDATA pin of the
write amplifier.
Fig.20 RDMUX, RDSYNC and TCLOCK timing.
handbook, full pagewidth
TCLOCK
RDSYNC
RDMUX
C
C
C
C
C
C
C
C
A
C
C
C
C
C
C
C
C
A
C
C
C
C
C
C
C
C
A
MGB396
Fig.21 WDATA and TCLOCK timing.
handbook, full pagewidth
WDATA
T
MGB397
T
T
T
T
T
T
T
T
T
T
T
SYNC
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