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參數資料
| 型號： | SAA3323GP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Drive processor for DCC systems |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80 |
| 文件頁數： | 27/56頁 |
| 文件大小： | 274K |
| 代理商： | SAA3323GP |
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May 1994
27
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
If SLEEP is ‘HIGH’ then the state of the SPEED signal will
be the state that it was in just before the SAA3323 went
into sleep. Thus if SPEED was HIGH just before sleep it
will stay HIGH during sleep. The same applies if it was
LOW or if it was in ‘high-Z’ state. Note that a reset of the
SAA3323 will take the SPEED signals out of ‘high-Z’ state.
Microcontroller connections
L3REF
This active LOW output pin indicates the start of a time
segment, it goes LOW for 5.2
μ
s once every 42.66 ms
approximately and can be used for generating interrups for
the microcontroller. If a re-synchronization occurs then the
time between the occurrences van vary. This pin can be
connected directly to the interrupt input of the
microcontroller.
L3CLK
This input pin is the clock line for the microcontroller
interface.
L3DATA
This input/output pin is the serial data line for the
microcontroller interface.
L3MODE
This input determines the type of transfer that is occurring
between the microcontroller and the SAA3323. If L3MODE
is LOW then a device address can be sent by the
microcontroller. If L3MODE is HIGH then a data transfer
may be occurring.
L3INT
This pin carries interrupts from the digital equalizer
module. It can also be programmed to reflect the state of
the AENV, LABEL and VIRGIN signals.
Table 21
Timing values for Fig.23.
Notes
1.
2.
T is the period of the master clock on the chip.
t
d4
is the delay time between the last bit of a byte and
first bit of the next byte, if no ‘halt’ is used.
SYMBOL
TIME
(1)
t
W1
t
d1
t
h2
t
d2
t
d5
t
cL
t
cH
t
su1
t
h1
t
d3
t
h3
t
d4
t
d4(2)
T + t
su (L3MODE)
+ t
h (L3MODE)
; t
w1
≥
200 ns
T + t
su (L3MODE)
+ t
h (L3CLK)
; t
d1
≥
200 ns
T + t
su (L3CLK)
+ t
h (L3MODE)
; t
h2
≥
200 ns
T + t
su (L3CLK)
+ t
d (L3DATA)
; t
d2
≤
250 ns
0
≤
t
d5
≤
50 ns
T + t
su (L3CLK)
+ t
h (L3CLK)
; t
cL
≥
200 ns
T + t
su (L3CLK)
+ t
h (L3CLK)
; t
cH
≥
200 ns
T + t
su (L3DATA)
+ t
h (L3CLK)
; t
su1
≤
200 ns
T + t
su (L3CLK)
+ t
h (L3DATA)
; t
h1
≤
35 ns
2
×
T + t
su (L3MODE)
+ t
d (L3DATA)
; t
d3
≤
250 ns
T + t
h (L3CLK)
+ t
d (L3DATA)
; t
h3
≥
50 ns
2
×
T + t
su (L3CLK)
+ t
d (L3DATA)
; t
d4
≤
410 ns
3
×
T + t
su (L3CLK)
+ t
d (L3DATA)
; t
d4
≤
575 ns
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