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參數(shù)資料
| 型號： | SAA3323GP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Drive processor for DCC systems |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80 |
| 文件頁數(shù)： | 10/56頁 |
| 文件大?。?/td> | 274K |
| 代理商： | SAA3323GP |
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May 1994
10
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Table 3
RAM settings by register SET3.
TFE
DATA STREAMS
The TFE module has three read/write data streams that
are accessible via the L3 interface and they are shown in
Table 4.
RAM
REGISTER SET3
RTYPE 0
RTYPE 1
RTim 0
RTim 1
bit 0
bit 1
bit 2
bit 3
Table 4
TFE data streams.
TFE ‘
COMMANDS
’
These are the commands that need to be sent to the TFE
in order to access the indirectly accessible registers and
the data streams, see Table 5.
DATA STREAM NAME
READ/WRITE
SYSINFO
AUXINFO
Scratch pad RAM
R/W
R/W
R/W
Table 5
TFE commands.
NAME
COMMAND BYTE
EXPLANATION
7
6
5
4
3
2
1
0
RDSPEED
LDSET0
LDSET1
LDSET2
LDSET3
LDSPDDTY
LDBYTCNT
LDRACCNT
RDAUX
RDSYS
RDDRAC
RDWDRAC
WRAUX
WRSYS
WRDRAC
WRWDRAC
0
0
0
0
0
0
0
0
0
0
Y
Y
0
0
Y
Y
0
0
0
0
0
0
0
0
0
0
Z
Z
0
0
Z
Z
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
1
1
0
0
1
0
1
0
1
0
1
read SPEED register
load new TFE settings register 0
load new TFE settings register 1
load new TFE settings register 2
load new TFE settings register 3
load SPDDTY register
load BYTCNT register
load RACCNT register
read AUXILIARY information
read SYSINFO
read RAM data bytes (8 bits) from quarter YZ
read RAM data words (12 bits) from quarter YZ
write AUXILIARY information
write SYSINFO
write RAM data bytes (8 bits) to quarter YZ
write RAM data words (12 bits) to quarter YZ
Digital equalizer module
The digital equalizer module has 2 basic modes of
operation as shown in Table 6.
Table 6
Basic modes of equalizer module.
MODE
EXPLANATION
Play
main data and AUX channels are
equalized
only AUX channel is processed; AUX
envelope information is processed
Search
D
IGITAL EQUALIZER REGISTERS
The digital equalizer module has 9 write only, 3 read only
and 1 read/write register(s) that are accessible via the
L3 interface, one write register (CMD) and 2 read registers
(STATUS0 and STATUS1) which are directly addressable,
the other registers are indirectly addressable via
commands sent to the CMD register. The registers are
named as shown in Table 7.
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