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參數(shù)資料
| 型號： | SAA3323 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Drive processor for DCC systems |
| 中文描述： | 戴納信貸驅(qū)動處理器的系統(tǒng) |
| 文件頁數(shù)： | 36/56頁 |
| 文件大?。?/td> | 274K |
| 代理商： | SAA3323 |
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May 1994
36
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Table 36
DEQSET digital equalizer settings.
Note
1.
ACup is the AUX envelope counter direction is up. This setting caused the AUX envelope counter increment or to
decrement by 1 every rising edge of the AUX envelope signal AENV.
BIT
7
0
6
0
5
0
4
0
3
0
2
1
0
Meaning
Default
ACup
(1)
0
DM1
0
DM0
0
Fig.29 CHTST1 and CHTST2 output timing.
handbook, full pagewidth
TCLOCK
CHTST
MCLK
0
1
2
3
4
5
6
7
0
1
2
3
LSB
MSB
MGB403
DM1 and DM0
Table 37
DM1 and DM0 digital equalizer mode of
operation.
Notes
1.
In normal mode the main data channels and the AUX
channel are processed (equalized), the AUX channel
envelope information is not processed.
In search mode only the AUX channel is processed by
the digital equalizer.
Off means that the digital equalizer is put to sleep (low
power), this can be used for example in portable
recording equipment. RDSYNC is HIGH if off mode.
Also note that the other digital equalizer registers are
not addressable while the digital equalizer is in off
mode.
2.
3.
DM
MODE OF OPERATION OF
DIGITAL EQUALIZER
1
0
0
0
1
1
0
1
0
1
normal
(1)
search
(2)
off
(3)
off
(3)
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