參數(shù)資料
型號(hào)： SAA3323
廠商： NXP Semiconductors N.V.
英文描述： Drive processor for DCC systems
中文描述： 戴納信貸驅(qū)動(dòng)處理器的系統(tǒng)
文件頁(yè)數(shù)： 12/56頁(yè)
文件大?。?/td> 274K
代理商： SAA3323
May 1994
12
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Table 11
SH1 and SH2 (FIR output scaling).
Transfer of FIR coefficients
For the main data channels (tracks 0 to 7) there are
10 coefficients (taps) each of 8 bits, where all of the data
channels make use of the same coefficients. The
addresses for the main data coefficients 0 to 9 are
0 to 9
dec
respectively.
There are ten coefficients (taps) each of 8 bits for the aux
channel (CHAUX). The addresses for the auxiliary
coefficients 0 to 9 are 16 to 25
dec
respectively.
SH
EFFECT ON FIR OUTPUT
1
0
0
0
0
1
FIR mod 256
mod 256
1
0
mod 256
1
1
mod 256
2
FIR
F4
8
FIR
There are 2 banks of coefficients for both the aux and the
main data channels, namely the ‘buffer’, and the ‘a(chǎn)ctive’
banks. The microcontroller writes only to the ‘buffer’
banks, and reads only from the ‘a(chǎn)ctive’ banks.
The microcontroller can poll the digital equalizer status bit
BKSW to see when the switch occurs. BKSW starts life
LOW, goes HIGH as a result of the bank switching and
goes LOW as result of the complete value of a main data
coefficient being received by the digital equalizer.
The microcontroller sets
μ
CS HIGH before sending the
new set of aux or main data coefficients, the digital
equalizer resets it once the bank switch occurs.
The actual FIR coefficients that are used are a function of
the tape head, read amplifier and type of tape (i.e.
pre-recorded or own recorded) used, such information is
outside of the scope of this data sheet.
Coefficient address counter (COEFCNT)
This 5 bit counter is used to point to the FIR coefficient to
be transferred to or from the digital equalizer.
Table 12
Coefficient address counter.
BIT
7
0
6
0
5
0
4
3
2
1
0
Meaning
Default
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
Pin explanations and interfacing to other hardware
RESET
This is an active HIGH input which resets the SAA3323
and brings it into its default mode, DPAP. This reset does
not affect the contents of the FIR filter coefficients in the
digital equalizer. This should be connected to the system
reset, which can be driven by the microcontroller. The
duration of the reset pulse should be at least 15
μ
s.
SLEEP
This pin is an active HIGH input which puts the SAA3323
in a low power consumption SLEEP mode. This pin should
be connected to the DCC SLEEP signal, which can be
driven by the microcontroller. The CLK24 clock may be
stopped and the VREFP and VREFN inputs brought to
ground while the SAA3323 is in ‘sleep’ mode to further
reduce power consumption. When recovering from sleep
mode, the SLEEP pin should be taken LOW and the
SAA3323 reset.
CLK24
This is the 24.576 MHz clock input and should be
connected directly to the SAA2003 (pin CLK24).
Sub-band serial PASC interface connections
The timing for the sub-band serial PASC interface is given
in Figs 5 to 7.
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