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參數(shù)資料
| 型號： | SAA3323 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Drive processor for DCC systems |
| 中文描述： | 戴納信貸驅動處理器的系統(tǒng) |
| 文件頁數(shù)： | 32/56頁 |
| 文件大?。?/td> | 274K |
| 代理商： | SAA3323 |
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May 1994
32
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
has been read will generate a new interrupt. Interrupts that are already noted in the digital equalizer Status 0 are cleared
by reading it.
Table 24
Digital equalizer STATUS0.
Notes
1.
BKSW (filter bank switched) indicates that the last main data coefficients sent to the digital equalizer have been
activated.
Vup indicates whether an interrupt caused by the rising edge of VIRGIN has occurred.
AEup indicates whether an interrupt caused by the rising edge of AUX envelope has occurred.
AEdn indicates whether an interrupt caused by the falling edge of AUX envelope has occurred
Lup indicates whether an interrupt caused by the rising edge of LABEL has occurred.
Ldn indicates whether an interrupt caused by the falling edge of LABEL has occurred.
ECZ indicates that the AUX envelope counter has reached zero.
2.
3.
4.
5.
6.
7.
BIT
7
6
5
4
3
2
1
0
Meaning
BKSW
(1)
TEST
Vup
(2)
AEup
(3)
AEdn
(4)
Lup
(5)
Ldn
(6)
ECZ
(7)
Fig.26 AUX channel envelope to AENV delays.
handbook, full pagewidth
tAUX
RDMUX
AENV
MGB400
d1
t
d2
t
Fig.27 AENV to LAB delays.
handbook, full pagewidth
AENV
(internal)
LAB
MGB401
td3
td4
tAUX
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