參數(shù)資料
型號(hào): SAA3323
廠商: NXP Semiconductors N.V.
英文描述: Drive processor for DCC systems
中文描述: 戴納信貸驅(qū)動(dòng)處理器的系統(tǒng)
文件頁(yè)數(shù): 33/56頁(yè)
文件大?。?/td> 274K
代理商: SAA3323
May 1994
33
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Table 25
Digital equalizer STATUS1.
Notes
1.
2.
3.
VIR gives the state of the VIRGIN signal.
AENV represents the state of the AENV signal.
LAB gives the state of the LAB signal.
BIT
7
6
5
4
3
2
1
0
Meaning
VIR
(1)
AENV
(2)
LAB
(3)
Fig.28 AENV to VIR delays.
handbook, full pagewidth
AENV
(internal)
Vir
MGB402
td5
td6
tAUX
AUX envelope count (AECNT) register
This 16 bit register is used for loading the AUX envelope
counter and for reading the state of that counter, it is
therefore readable and writable as 2 bytes. Least
Significant Byte first.
Table 26
AECNT register.
Search speed (SSPD) register
Table 27
Search speed register.
Notes
1.
2.
3.
SVF speed validation flag, if HIGH then the search speed measurement is invalid.
SV4 to SV0 search speed value.
SR1 and SR0 search speed range.
AECNT
LEAST SIGNIFICANT BYTE
MOST SIGNIFICANT BYTE
BIT
7
2
7
6
2
6
5
2
5
4
2
4
3
2
3
2
2
2
1
2
1
0
2
0
7
6
5
4
3
2
1
2
9
0
2
8
Meaning
2
15
2
14
2
13
2
12
2
11
2
10
BIT
7
6
5
4
3
2
1
0
Meaning
SVF
(1)
SV4
(2)
SV3
(2)
SV2
(2)
SV1
(2)
SV0
(2)
SR1
(3)
SR0
(3)
Search speed
2
SR
SV
×
normal speed
×
=
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