
January 1995
5
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
SAA2501
6
PINNING
SYMBOL
PIN
DESCRIPTION
TYPE
RESET
FSCLK
FSCLKIN
MCLK
V
DD1
GND1
MCLKOUT
MCLKIN
X22OUT
X22IN
STOP
URDA
CDMWS
CDMEF
CDM
CDMCL
GND2
CDSCL
CDS
CDSEF
CDSWA
CDSSY
L3CLK
L3DATA
L3MODE
SD
FDEF
GND3
SCK
WS
FDAO
FDAI
FDFSY
V
DD2
TC1
TC0
TDO
TRST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
master reset input
sample rate clock output; buffered signal
sample rate clock signal input (see Table 1)
master clock output; buffered signal
supply voltage 1
ground 1
master clock oscillator output
master clock oscillator input or signal input
22.579 MHz clock oscillator output
22.579 MHz clock oscillator input or signal input
stop decoding input
unreliable data input; interrupt decoding
coded data (master input) word select output
coded data (master input) error flag input
ISO/MPEG coded data (master input)
coded data (master input) bit clock output
ground 2
coded data (slave input) bit clock
ISO/MPEG or EU147 (see Table 8) coded data (slave input)
coded data (slave input) error flag
coded data (slave input) burst window signal
coded data (slave input) frame sync
L3 interface bit clock input
L3 interface serial data input/output
L3 interface address/data select input
baseband audio I
2
S data output
filter data error flag output
ground 3
baseband audio data I
2
S clock output
baseband audio data I
2
S word select output
filter data output
filter data input
filter data output frame sync
supply voltage 2
do not connect; factory test control 1 input, with integrated pull-down resistor
do not connect; factory test control 0 input, with integrated pull-down resistor
boundary scan test data output
boundary scan test reset input; this pin should be connected to ground for
normal operation
boundary scan test clock input
I
O
I
O
O
I
O
I
I
I
O
I
I
O
I
I
I
I
I
I
I/O
I
O
O
O
O
O
I
O
I
I
O
I
TCK
39
I