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型號(hào)：	S83C154DXXX-12
廠商：	ATMEL CORP
元件分類(lèi)：	微控制器/微處理器
英文描述：	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁(yè)數(shù)：	698/1021頁(yè)
文件大?。?/td>	15196K
代理商：	S83C154DXXX-12

32072H–AVR32–10/2012

AT32UC3A3

FIFOCON: FIFO Control

For control endpoints:

The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them on these endpoints. When read,

their value is always 0.

For IN endpoints:

This bit is set when the current bank is free, at the same time as TXINI.

This bit is cleared (by writing a one to the FIFOCONC bit) to send the FIFO data and to switch to the next bank.

For OUT endpoints:

This bit is set when the current bank is full, at the same time as RXOUTI.

This bit is cleared (by writing a one to the FIFOCONC bit) to free the current bank and to switch to the next bank.

KILLBK: Kill IN Bank

This bit is set when the KILLBKS bit is written to one. This will kill the last written bank.

This bit is cleared by hardware after the completion of the “kill packet procedure”.

The user shall wait for this bit to be cleared before trying to process another IN packet.

Caution: The bank is cleared when the “kill packet” procedure is completed by the USBB core :

If the bank is really killed, the NBUSYBK field is decremented.

If the bank is not “killed” but sent (IN transfer), the NBUSYBK field is decremented and the TXINI flag is set. This specific case

can occur if at the same time an IN token is coming and the user wants to kill this bank.

Note : If two banks are ready to be sent, the above specific case can not occur, because the first bank is sent (IN transfer) while

the last bank is killed.

NBUSYBKE: Number of Busy Banks Interrupt Enable

This bit is set when the NBUSYBKES bit is written to one. This will enable the Number of Busy Banks interrupt (NBUSYBK).

This bit is cleared when the NBUSYBKEC bit is written to zero. This will disable the Number of Busy Banks interrupt

ERRORTRANSE: Transaction Error Interrupt Enable

This bit is set when the ERRORTRANSES bit is written to one. This will enable the transaction error interrupt (ERRORTRANS).

This bit is cleared when the ERRORTRANSEC bit is written to one. This will disable the transaction error interrupt

(ERRORTRANS).

DATAXE: DataX Interrupt Enable

This bit is set when the DATAXES bit is written to one. This will enable the DATAX interrupt. (see DTSEQ bits)

This bit is cleared when the DATAXEC bit is written to one. This will disable the DATAX interrupt.

MDATAE: MData Interrupt Enable

This bit is set when the MDATAES bit is written to one. This will enable the Multiple DATA interrupt. (see DTSEQ bits)

This bit is cleared when the MDATAEC bit is written to one. This will disable the Multiple DATA interrupt.

SHORTPACKETE: Short Packet Interrupt Enable

This bit is set when the SHORTPACKETES bit is written to one. This will enable the Short Packet interrupt (SHORTPACKET).

This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Short Packet interrupt

(SHORTPACKET).

STALLEDE: STALLed Interrupt Enable

This bit is set when the STALLEDES bit is written to one. This will enable the STALLed interrupt (STALLEDI).

This bit is cleared when the STALLEDEC bit is written to one. This will disable the STALLed interrupt (STALLEDI).

CRCERRE: CRC Error Interrupt Enable

This bit is set when the CRCERRES bit is written to one. This will enable the CRC Error interrupt (CRCERRI).

This bit is cleared when the CRCERREC bit is written to one. This will disable the CRC Error interrupt (CRCERRI).

OVERFE: Overflow Interrupt Enable

This bit is set when the OVERFES bit is written to one. This will enable the Overflow interrupt (OVERFI).

This bit is cleared when the OVERFEC bit is written to one. This will disable the Overflow interrupt (OVERFI).

NAKINE: NAKed IN Interrupt Enable

This bit is set when the NAKINES bit is written to one. This will enable the NAKed IN interrupt (NAKINI).

This bit is cleared when the NAKINEC bit is written to one. This will disable the NAKed IN interrupt (NAKINI).

HBISOFLUSHE: High Bandwidth Isochronous IN Flush Interrupt Enable

This bit is set when the HBISOFLUSHES bit is written to one. This will enable the HBISOFLUSHI interrupt.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S83C154-L16	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
S83C154T-12	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
S83C154T-16	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
S83C154T-20	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
S83C154T-25	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller

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