亚洲精品在看在线观看,人妻无码中文专区久久av

您好，
買(mǎi)賣(mài)IC網(wǎng)歡迎您。
請(qǐng)登錄
免費(fèi)注冊(cè)

您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄25635 > S83C154DXXX-12 (ATMEL CORP) 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44 PDF資料下載

型號(hào)：	S83C154DXXX-12
廠商：	ATMEL CORP
元件分類(lèi)：	微控制器/微處理器
英文描述：	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁(yè)數(shù)：	257/1021頁(yè)
文件大小：	15196K
代理商：	S83C154DXXX-12

32072H–AVR32–10/2012

AT32UC3A3

The user must also make sure that the system stack is large enough so that any event is able to

push the required registers to stack. If the system stack is full, and an event occurs, the system

will enter an UNDEFINED state.

Exceptions and Interrupt Requests

When an event other than scall or debug request is received by the core, the following actions

are performed atomically:

The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and

GM bits in the Status Register are used to mask different events. Not all events can be

masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and

Bus Error) can not be masked. When an event is accepted, hardware automatically

sets the mask bits corresponding to all sources with equal or lower priority. This inhibits

acceptance of other events of the same or lower priority, except for the critical events

listed above. Software may choose to clear some or all of these bits after saving the

necessary state if other priority schemes are desired. It is the event source’s respons-

ability to ensure that their events are left pending until accepted by the CPU.

When a request is accepted, the Status Register and Program Counter of the current

context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, reg-

isters R8-R12 and LR are also automatically stored to stack. Storing the Status

current event handling is completed. When exceptions occur, both the EM and GM bits

are set, and the application may manually enable nested exceptions if desired by clear-

ing the appropriate bit. Each exception handler has a dedicated handler address, and

this address uniquely identifies the exception source.

The Mode bits are set to reflect the priority of the accepted event, and the correct regis-

ter file bank is selected. The address of the event handler, as shown in Table 4-4, is

loaded into the Program Counter.

The execution of the event handler routine then continues from the effective address calculated.

The rete instruction signals the end of the event. When encountered, the Return Status Register

and Return Address Register are popped from the system stack and restored to the Status Reg-

ister and Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3,

registers R8-R12 and LR are also popped from the system stack. The restored Status Register

contains information allowing the core to resume operation in the previous execution mode. This

concludes the event handling.

Supervisor Calls

The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is

designed so that privileged routines can be called from any context. This facilitates sharing of

code between different execution modes. The scall mechanism is designed so that a minimal

execution cycle overhead is experienced when performing supervisor routine calls from time-

critical event handlers.

The scall instruction behaves differently depending on which mode it is called from. The behav-

iour is detailed in the instruction set reference. In order to allow the scall routine to return to the

correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC

CPU, scall and rets uses the system stack to store the return address and the status register.

Debug Requests

The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by

the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the

相關(guān)PDF資料	PDF描述
SC80C52XXX-12SV	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40
MR80C52CXXX-12/883:D	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44
MC80C52EXXX-12SC	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40
MD80C52TXXX-16SHXXX:D	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40
MR80C52CXXX-12SCR	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S83C154-L16	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
S83C154T-12	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
S83C154T-16	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
S83C154T-20	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
S83C154T-25	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller

發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

*型號(hào)	*數(shù)量	廠商	批號(hào)	封裝

采購(gòu)需求

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

我的聯(lián)系方式

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)