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型號：	S83C154DXXX-12
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁數(shù)：	697/1021頁
文件大?。?/td>	15196K
代理商：	S83C154DXXX-12

32072H–AVR32–10/2012

AT32UC3A3

Endpoint n Control Register

Register Name:

UECONn, n in [0..7]

Access Type:

0x01C0 + (n * 0x04)

Reset Value:

STALLRQ: STALL Request

This bit is set when the STALLRQS bit is written to one. This will request to send a STALL handshake to the host.

This bit is cleared when a new SETUP packet is received or when the STALLRQC bit is written to zero.

RSTDT: Reset Data Toggle

This bit is set when the RSTDTS bit is written to one. This will clear the data toggle sequence, i.e., set to Data0 the data toggle

sequence of the next sent (IN endpoints) or received (OUT endpoints) packet.

This bit is cleared instantaneously.

The user does not have to wait for this bit to be cleared.

NYETDIS: NYET token disable

This bit is set when the NYETDISS bit is written to one. This will send a ACK handshake instead of a NYET handshake in high-

This bit is cleared when the NYETDISC bit is written to one.This will let the USBB handling the high-speed handshake following

the usb 2.0 standard.

EPDISHDMA: Endpoint Interrupts Disable HDMA Request Enable

This bit is set when the EPDISHDMAS is written to one. This will pause the on-going DMA channel n transfer on any Endpoint n

interrupt (EPnINT), whatever the state of the Endpoint n Interrupt Enable bit (EPnINTE).

The user then has to acknowledge or to disable the interrupt source (e.g. RXOUTI) or to clear the EPDISHDMA bit (by writing a

one to the EPDISHDMAC bit) in order to complete the DMA transfer.

In ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA transfer is

running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but the new-packet DMA

transfer will not start (not requested).

If the interrupt is not associated to a new system-bank packet (NAKINI, NAKOUTI, etc.), then the request cancellation may

occur at any time and may immediately pause the current DMA transfer.

This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to complete a

DMA transfer by software after reception of a short packet, etc.

相關(guān)PDF資料	PDF描述
SC80C52XXX-12SV	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40
MR80C52CXXX-12/883:D	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44
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MD80C52TXXX-16SHXXX:D	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40
MR80C52CXXX-12SCR	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S83C154-L16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S83C154T-12	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S83C154T-16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S83C154T-20	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S83C154T-25	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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