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型號(hào)：	S80C32XXX-40R
廠商：	TEMIC SEMICONDUCTORS
元件分類(lèi)：	微控制器/微處理器
英文描述：	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
文件頁(yè)數(shù)：	978/1021頁(yè)
文件大?。?/td>	15196K
代理商：	S80C32XXX-40R

32072H–AVR32–10/2012

AT32UC3A3

10. Interrupt Controller (INTC)

Rev: 1.0.1.5

Features

Autovectored low latency interrupt service with programmable priority

– 4 priority levels for regular, maskable interrupts

– One Non-Maskable Interrupt

Up to 64 groups of interrupts with up to 32 interrupt requests in each group

Overview

The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an inter-

rupt request and an autovector to the CPU. The AVR32 architecture supports 4 priority levels for

regular, maskable interrupts, and a Non-Maskable Interrupt (NMI).

The INTC supports up to 64 groups of interrupts. Each group can have up to 32 interrupt request

lines, these lines are connected to the peripherals. Each group has an Interrupt Priority Register

(IPR) and an Interrupt Request Register (IRR). The IPRs are used to assign a priority level and

an autovector to each group, and the IRRs are used to identify the active interrupt request within

each group. If a group has only one interrupt request line, an active interrupt group uniquely

identifies the active interrupt request line, and the corresponding IRR is not needed. The INTC

also provides one Interrupt Cause Register (ICR) per priority level. These registers identify the

group that has a pending interrupt of the corresponding priority level. If several groups have a

pending interrupt of the same level, the group with the lowest number takes priority.

Block Diagram

Figure 10-1 gives an overview of the INTC. The grey boxes represent registers that can be

accessed via the user interface. The interrupt requests from the peripherals (IREQn) and the

NMI are input on the left side of the figure. Signals to and from the CPU are on the right side of

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